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US 8,569,185 B2Granted
Method of fabricating gate electrode using a treated hard mask
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMatt Yeh, Hui Ouyang, Han-Pin Chung, Shiang-Bau Wang
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Abstract
A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.
Claims20
A method of fabricating an integrated circuit device, the method comprising:
- providing a substrate;
- forming a polysilicon material layer over the substrate;
- forming a hard mask layer over the polysilicon material layer;
- providing a treatment to the hard mask layer to introduce species therein, wherein the species has an atomic number less than about 50, wherein the species is introduced by an ion implantation that is performed with a dose of less than or equal to about 1E14 atoms/cm2;
- patterning the treated hard mask layer;
- and
- patterning the polysilicon material layer with the patterned treated hard mask layer.
4 more elements
A method comprising:
- providing a substrate;
- forming a gate electrode layer over the substrate, the gate electrode layer including polysilicon;
- forming a hard mask layer over the gate electrode layer;
- heating the hard mask layer to form a heated hard mask layer;
- ion implanting the heated hard mask layer to form a treated hard mask layer, wherein ion implanting the heated hard mask includes implanting a species selected from the group consisting of fluorine, nitrogen, phosphorous, arsenic, and indium into the heated hard mask layer;
- patterning the treated hard mask layer and the gate electrode layer to form a gate structure of a PMOS device and a gate structure of an NMOS device;
- forming n-type strained source/drain regions in the substrate, wherein the n-type strained source/drain regions are adjacent to the edges of the gate structure of NMOS device;
- forming p-type strained source/drain regions in the substrate, wherein the p-type strained source/drain regions are adjacent to the edges of the gate structure of PMOS device;
- forming n-type lightly-doped source/drain regions in the n-type strained source/drain regions by a first tilt-angle ion implantation;
- and
- forming p-type lightly-doped source/drain regions in the p-type strained source/drain regions by a second tilt-angle ion implantation.
8 more elements
A method comprising:
- providing a substrate;
- forming a gate electrode material layer over the substrate;
- forming a hard mask layer over the gate electrode material layer;
- performing an ion implantation process on the hard mask layer to introduce ion species therein, wherein the species has an atomic number less than about 50, wherein the species is introduced by an ion implantation that is performed with a dose of less than or equal to about 1E14 atoms/cm2;
- and
- patterning the hard mask and the gate electrode material layer to form a gate stack.
3 more elements
Dependencies are inferred from the claim text.