CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication

A semiconductor structure comprising:

• a substrate comprising a first active region including a first crystallographic orientation material and a second active region including a second crystallographic orientation material, wherein a first upper surface of the first crystallographic orientation material is vertically offset and located beneath a second upper surface of the second crystallographic orientation material, wherein the second crystallographic orientation material has a different crystalline orientation than the first crystallographic orientation material;
• an isolation region located between the first active device region and the second active device region, wherein said isolation region has a topmost that is vertically offset and located above a recessed surface of the isolation region, wherein said topmost surface of said isolation region is coplanar with said second upper surface of the second crystallographic orientation material;
• and
• a p-type field effect transistor including a first gate located within the first active region and an n-type field effect transistor including a second gate located within the second active region, where an upper surface of the first gate and an upper surface of the second gate are coplanar, and a first gate dielectric of the first gate is in direct contact with the first upper surface, and a second gate dielectric of the second gate is in direct contact with the second upper surface.