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US 8,569,125 B2Granted
FinFET with improved gate planarity
AssigneeInternational Business Machines Corporation
InventorsTheodorus Eduardus Standaert, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Soon-Cheon Seo, Tenko Yamashita
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Abstract
A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged.
Claims15
A method of fabricating a FinFET, comprising:
- forming a pattern of fins, wherein each fin comprises a fin hardmask layer disposed thereon;
- depositing a gate layer over the pattern of fins;
- depositing a gate hardmask layer over the gate layer;
- removing a portion of the gate hardmask layer and the gate layer, thereby exposing the pattern of fins;
- depositing an etch-resistant layer over a first subset of fins from the pattern of fins;
- removing a second subset of the fins from the pattern of fins with an etch;
- and
- merging at least some of the first subset of fins.
5 more elements
A method of fabricating a FinFET, comprising:
- forming a pattern of fins, wherein each fin comprises a fin hardmask layer disposed thereon;
- removing the fin hardmask layer from a first subset of fins from the pattern of fins;
- depositing a gate layer over the pattern of fins;
- depositing a gate hardmask layer over the gate layer;
- removing a portion of the gate hardmask layer;
- removing a portion of the gate layer and the first subset of fins in a single process step, wherein a second subset of fins from the pattern of fins is preserved.
3 more elements
Dependencies are inferred from the claim text.