Method for fabricating a flash memory cell utilizing a high-K metal gate process and related structure
AssigneeBroadcom Corporation
InventorsWei Xia, Xiangdong Chen, Frank Hui
Life of this patent
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Abstract
According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.
Claims20
A semiconductor die comprising:
- a flash memory cell including a control gate stack overlying a floating gate stack in a memory region of a substrate;
- said floating gate stack including a floating gate overlying a portion of a dielectric one layer;
- said floating gate comprising a portion of a metal one layer and said dielectric one layer comprising a first high-k dielectric material;
- wherein said control gate stack includes a control gate comprising a polysilicon segment overlying a metal two segment.
A semiconductor die comprising:
- a flash memory cell including a control gate stack overlying a floating gate stack;
- said floating gate stack including a floating gate overlying a portion of a dielectric layer;
- said floating gate comprising a portion of a metal layer;
- said dielectric layer comprising a first high-k dielectric material;
- wherein said control gate stack includes a control gate comprising a polysilicon segment overlying a metal two segment.
A semiconductor die comprising:
- a flash memory cell including a control gate stack overlying a floating gate stack in a memory region of a substrate;
- said floating gate stack including a floating gate overlying a portion of a dielectric one layer;
- said floating gate comprising a portion of a metal one layer and said dielectric one layer comprising a first high-k dielectric material;
- said control gate stack including a control gate comprising a portion of a metal two layer;
- a first gate stack in a first FET region of said substrate, wherein said first gate stack includes a first gate comprising another portion of said metal one layer;
- a second gate stack in a second FET region of said substrate, wherein said second gate stack includes a second gate comprising another portion of said metal two layer.
Dependencies are inferred from the claim text.