Strained transistor with optimized drive current and method of forming

A semiconductor device formed in a semiconductor substrate comprising:

• a first PMOS transistor formed in a P-type active region, the first PMOS transistor comprising a first poly gate electrode overlying the P-type active region;
• an first NMOS transistor formed in an N-type active region, the first NMOS transistor comprising a second poly gate electrode overlying said N-type active region;
• and
• a first compressive-stress layer substantially conformally over the first poly gate electrode and the P-type active region;
• wherein a first shortest distance in a first direction parallel with a current flow of the first PMOS transistor and between the first poly gate electrode and a first outermost edge of the first compressive-stress layer is greater than 0.4 um, wherein at least a portion of the first outermost edge of the first compressive-stress layer is located over the P-type active region;
• wherein a second shortest distance in a second direction perpendicular with the current flow of the first PMOS transistor and between the P-type active region and a second outermost edge of the first compressive-stress layer is in a range of between about 60 nm to about 400 nm.

A PMOS transistor formed in a P-type active region (OD) in a semiconductor substrate comprising:

• a gate region overlying the OD region having a poly gate electrode on the top;
• a source and drain region formed on the opposite side of the gate region, substantially aligned with an edge of the gate region and the edges of the OD region;
• a compressive-stress layer substantially conformally over the gate electrode and the OD region, the compressive-stress layer having a first and second edge, wherein the first edge is an outermost edge of the compressive-stress layer;
• wherein the space between an edge of the gate electrode and the first edge of the compressive-stress layer is in the range of one to two times either P or G, whichever is larger, where P is the minimum design rule gate poly to P-type OD dimension, and G is the minimum design rule poly-to-poly spacing on a P-type OD region;
• and
• wherein the space between a P-type OD edge and the second edge of the compressive-stress layer is in the range of between about one-third to about two-thirds of the sum of L and H, where L is the minimum P-type OD to N-well boundary dimension and H is the minimum spacing between an N-type OD and an N-well boundary;
• and
• wherein the compressive-stress layer has at least a portion of the first edge located over the OD region.