Isolation method and package using a high isolation differential ball grid array (BGA) pattern
AssigneeThe Boeing Company
InventorLouis Catuogno
Life of this patent
Estimating the term…
Abstract
According to an embodiment an improved Application Specific Integrated Circuit (ASIC) isolation method and system for assigning signal pins in an ASIC package having a plurality of signal pins is disclosed. The method and system comprise identifying an isolation requirement of the ASIC and determining an optimized pattern for substantially diagonal pairing of signal pins in relation to the isolation requirement. The method includes pairing signal pairs substantially diagonally in accordance with the pattern.
Claims17
A computer based method to arrange signal pins for pairing in an integrated circuit, comprising:
- determining, in a computer system, an isolation requirement and an area for the integrated circuit;
- determining, in the computer system, a signal pin pattern that satisfies the isolation requirement within the area by repetitively performing operations, comprising:
- determining, in the computer system, available signal and ground pin pairs within the area for the integrated circuit;
- identifying, in the computer system, two diagonally adjacent signal pins;
- assigning, in the computer system, the two diagonally adjacent signal pins as a first diagonally adjacent signal pin pair;
- identifying, in the computer system, a diagonal reference line which extends perpendicularly from the first signal pin pair;
- identifying, in the computer system, a closest pair of signal pins which reside on the diagonal reference line;
- and
- adding, in the computer system, the closest pair of signal pins to the layout.
A computer based method to determine an integrated circuit signal pin layout by performing operations, comprising:
- (a) determining, in a computer system, available signal and ground pin pairs within the area for the integrated circuit;
- (b) identifying, in the computer system, two diagonally adjacent signal pins;
- (c) assigning, in the computer system, the two diagonally adjacent signal pins as a diagonally adjacent signal pin pair;
- (d) identifying, in the computer system, a diagonal reference line which extends perpendicularly from the diagonally adjacent signal pin pair;
- (e) identifying, in the computer system, a closest pair of signal pins which reside on the diagonal reference line;
- (f) adding, in the computer system, the closest pair of signal pins to the layout;
- (g) identifying, in the computer system, signal pins proximate the first diagonally adjacent signal pin pair which do not lie on the diagonal reference line;
- and
- (h) moving, in the computer system, the signal pins away from the first adjacent signal pin pair.
A computer-based system to generate an integrated circuit signal pin layout by implementing operations, comprising:
- (a) determining, in the computer system, available signal and ground pin pairs within the area for the integrated circuit;
- (b) identifying, in the computer system, two diagonally adjacent signal pins;
- (c) assigning, in the computer system, the two diagonally adjacent signal pins as a diagonally adjacent signal pin pair;
- (d) identifying, in the computer system, a diagonal reference line which extends perpendicularly from the diagonally adjacent signal pin pair;
- (e) identifying, in the computer system, a closest pair of signal pins which reside on the diagonal reference line;
- (f) adding, in the computer system, the closest pair of signal pins to the layout;
- (g) identifying, in the computer system, signal pins proximate the first diagonally adjacent signal pin pair which do not lie on the diagonal reference line;
- and
- (h) moving, in the computer system, the signal pins away from the first adjacent signal pin pair.
Dependencies are inferred from the claim text.