Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns

A computer-executed method for decomposing a circuit design layout to decomposed layouts for a multiple patterning lithographic technique, the method comprising:

• providing a library of prior patterns, including a category of forbidden patterns;
• scanning the circuit design layout and proposing a plurality of patterns for the decomposed layouts;
• comparing the plurality of patterns with the library of prior patterns;
• if a selected proposed pattern from the plurality of patterns matches a forbidden pattern, eliminating the selected proposed pattern from the plurality of patterns;
• communicating detailed decomposition information associated with a chosen pattern from the plurality of patterns to a decomposition tool;
• generating the decomposed layouts from the detailed decomposition information;
• fabricating a plurality of masks from the decomposed layouts;
• and
• performing a multiple patterning lithographic technique with the plurality of masks on a semiconductor substrate.

A method for fabricating a plurality of masks for a multiple patterning lithographic technique, the method comprising:

• providing a library of prior patterns, including a category of forbidden patterns and a category of preferred patterns;
• scanning a circuit design layout for the semiconductor device and proposing patterns for decomposed layouts;
• comparing the proposed patterns with the library of prior patterns;
• if a selected proposed pattern matches a forbidden pattern, eliminating the selected proposed pattern;
• if the selected proposed pattern matches a preferred pattern, identifying the selected proposed pattern for use in the decomposed layouts;
• communicating detailed decomposition information associated with the preferred pattern matched with the identified proposed pattern to a decomposition tool;
• generating the decomposed layouts from the detailed decomposition information;
• fabricating the plurality of masks from the decomposed layouts;
• and
• performing the multiple patterning lithographic technique with the plurality of masks on a semiconductor substrate.