Method for fabricating a semiconductor device using a modeling algorithm to model the proximity effect from the sub-layer
AssigneeSamsung Electronics Co., Ltd.
InventorNo Young Chung
Life of this patent
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Abstract
A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography.
Claims26
A method for forming a circuit layout, comprising:
- performing first proximity effect modeling based on photolithography proximity effects caused by a first layer by using a computer, wherein the first layer comprises a gate poly and a field poly formed on a substrate;
- performing second proximity effect modeling based on photolithography proximity effects caused by a second layer, wherein the second layer comprises an active layer positioned under the gate poly, and wherein performing the second proximity effect modeling includes calculating a pattern density of the active layer by using a computer;
- combining results of the first and second proximity effect modeling using a modeling algorithm by using a computer;
- performing proximity correction using the combined results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography by using a computer:
- inputting the circuit layer to a processor;
- generating a target based on the inputted circuit layout;
- performing the proximity correction on the generated target;
- and
- outputting the manipulated mask layout.
A computer program product embodied in one or more non-transitory computer readable storage mediums having computer readable program code embodied thereon to perform a method for forming a circuit layout, the method comprising:
- performing first proximity effect modeling based on photolithography proximity effects caused by a first layer, wherein the first layer comprises a gate poly and a field poly formed on a substrate;
- performing second proximity effect modeling based on photolithography proximity effects caused by a second layer, wherein the second layer comprises an active layer positioned under the gate poly, and wherein performing the second proximity effect modeling includes calculating a pattern density of the active layer;
- combining results of the first and second proximity effect modeling using a modeling algorithm;
- performing proximity correction using the combined results to manipulate a layout of a mask used when forming the circuit layout by photolithography:
- inputting the circuit layout to a processor;
- generating a target based on the inputted circuit layout;
- performing the proximity correction on the generated target;
- and
- outputting the manipulated mask layout.
A method for forming a circuit layout, comprising:
- performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer by using a computer;
- incorporating results of the process proximity effect modeling into a modeling algorithm by using a computer;
- performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography by using a computer:
- inputting the circuit layout to a processor;
- generating a target based on the inputted circuit layout;
- performing the proximity correction on the generated target;
- and
- outputting the manipulated mask layout.
Dependencies are inferred from the claim text.