System and circuit for simulating gate-to-drain breakdown
AssigneeTexas Instruments Incorporated
InventorsPaul E. Nicollian, Riza T. Cakici
Life of this patent
Estimating the term…
Abstract
A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.
Claims22
A circuit simulation system, comprising:
- a processor;
- and
- a circuit simulator module that when executed causes the processor to simulate operation of an electronic circuit;
- the circuit simulator module comprising:
- a field effect transistor (FET) model, the FET model configured to emulate a FET in a condition of dielectric breakdown, the FET model comprising models of:
- a primary FET;
- a first depletion mode FET and a second depletion mode FET connected between a gate and a drain of the primary FET;
- wherein a gate and a drain of the first depletion mode FET are connected to the gate of the primary FET, and a gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.
A non-transitory computer-readable storage medium encoded with a field effect transistor (FET) model that causes a computer to simulate:
- a primary FET;
- and
- two depletion mode FETs operating in saturation between a gate and a drain of the primary FET;
- wherein the depletion mode FETs provide a polarity symmetric gate current and emulate a power law exponent.
A method, comprising:
- simulating, by a computer, operation of a field effect transistor (FET);
- the simulating comprising:
- computing, by the computer, signal values based on a model of the FET, the model emulating:
- a primary FET;
- and
- a first and a second depletion mode FET operating in saturation between a gate and a drain of the primary FET;
- a gate and a drain of the first depletion mode FET being connected to the gate of the primary FET, and a gate and a drain of the second depletion mode FET being connected to the drain of the primary FET.
A circuit comprising:
- a primary field effect transistor (FET);
- and
- a first depletion mode FET and a second depletion mode FET connected between a gate and a drain of the primary FET;
- wherein a gate and a drain of the first depletion mode FET are connected to the gate of the primary FET, and a gate and a drain of the second depletion mode FET are connected to the drain of the primary FET;
- wherein the first depletion mode FET and a second depletion mode FET operate in saturation.
Dependencies are inferred from the claim text.