Semiconductor device
AssigneePanasonic Corporation
InventorsJunichi Shimada, Hidenori Shibata, Tsutomu Fujii, Hiromasa Fukazawa, Nobuyuki Iwauchi, Takeya Fujino
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Abstract
Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern (21) is formed in relatively narrow wiring void (Area_S1) so as to extend in a direction different from that of dummy patterns (22, 23) formed in relatively wide wiring void (Area_S2).
Claims11
A semiconductor device having a multilayer wiring structure, comprising a first wiring layer including a plurality of wirings and a plurality of dummy patterns, wherein
- a plurality of wiring voids is included in the first wiring layer, each of the plurality of wiring voids formed between a first and second ones of the plurality of wirings,
- the plurality of dummy patterns is formed in the plurality of wiring voids in the first wiring layer,
- the plurality of wiring voids comprises a relatively narrow wiring void and a relatively wide wiring void,
- the plurality of dummy patterns includes a first predetermined number of dummy patterns formed in the relatively narrow wiring void and extending in a first direction in the first wiring layer and a second predetermined number of dummy patterns formed in the relatively wide wiring void and extending in a second direction perpendicular to the first direction in the first wiring layer.
Dependencies are inferred from the claim text.