System, processor, apparatus and method for inter-processor communication

A processor adapted to be included in a multi-processor system, wherein the processor is a receiving processor adapted to receive a data message containing a payload portion, a size of the payload portion, and an index, and wherein the multiprocessor system further comprises a sending processor, adapted to send the data message, and a memory unit associated with the receiving processor, said processor comprising:

• mapping circuitry comprising a pointer array for storing pointers, an index register, and a pointer register, and being adapted to map the index contained in the data message received from the sending processor to a pointer, wherein the pointer is associated with a buffer of the memory unit;
• a direct memory access controller adapted to execute scatter chains comprising at least one peripheral-to-memory transfer and at least one memory-to-memory transfer;
• an input buffer associated with a data link, and being adapted to receive the data message containing the size, the index, and the payload portion;
• the receiving processor being adapted to write the payload portion of the received data message to the buffer as indicated by the pointer, and
• wherein the direct memory access controller is further adapted to:
• read the size from the input buffer;
• read the index from the input buffer;
• write the index to the index register;
• write the pointer to the pointer register;
• read the pointer, associated with the buffer of the memory unit, from the pointer register;
• read the payload portion from the input buffer;
• and
• write the payload portion to the buffer of the memory unit as indicated by the pointer.

A method of receiving a data message at a processor, wherein the data message contains a size, an index, and a payload portion, the method comprising:

• reading the size from an input buffer of the processor;
• reading the index from the input buffer;
• mapping the index to a pointer, wherein mapping the index to the pointer comprises:
• writing the index to an index register;
• mapping the index to the pointer;
• writing the pointer to a pointer register;
• and
• reading the pointer from the pointer register;
• reading the payload portion from the input buffer;
• and
• writing the payload portion to a buffer of a memory associated with the processor,
• wherein the buffer of the memory is indicated by the pointer.