Compiler, compile method, and processor core control method and processor

A compiler which is stored in a non transitory computer-readable media, compiles a source code, and is implemented in a plurality of processor cores, the compiler comprising:

• a parallel loop processing detection unit configured to detect from the source code a parallel loop processing code in which an internal processing operation is executed for a given number of repeating times and internal processing operations to be executed for the given number of repeating times are independent of each other and are parallelizable;
• and
• a dynamic parallel conversion unit configured to generate a control core code for control of the number of repeating times in the parallel loop processing code and a parallel processing code for changing the number of repeating times corresponding to the control from the control core code, wherein the control core code generated by the dynamic parallel conversion unit is configured by:
• a parallelism selection code for calculation of a number of processor cores which perform a process of the parallel processing code and for acquisition of a result as a number of divided loops;
• a power control code for selection of the processor core used on a basis of the number of divided loops, and calculation of an operation clock for each selected processor core;
• and
• an iteration number analysis code for calculation of a number of iteration times as the number of repeating times for each processor core used on a basis of the number of divided loops and a starting position of the iteration, and for definition of a calculation result as iteration information, and wherein
• when a disturbance interrupting process occurs during execution of the parallel loop processing code, the number of repeating times is recalculated for each processor core to execute the parallel loop processing code other than processor cores necessary for executing the disturbance interrupting process.

A non-transitory computer-readable storage medium storing a program used to direct a computer to execute a process for compiling a source code implemented in a plurality of processor cores, the process comprising:

• detecting from the source code a parallel loop processing code in which an internal processing operation is executed for a given number of repeating times and internal processing operations to be executed for the given number of repeating times are independent of each other and are parallelizable;
• generating a control core code for control of the number of repeating times in the parallel loop processing code and a parallel processing code for changing the number of repeating times corresponding to the control from the control core code;
• calculating a number of processor cores which perform a process of the parallel processing code and for acquisition of a result as a number of divided loops;
• selecting the processor core used on a basis of the number of divided loops, and calculation of an operation clock for each selected processor core;
• calculating a number of iteration times as the number of repeating times for each processor core used on a basis of the number of divided loops and a starting position of the iteration, and for definition of a calculation result as iteration information, and
• recalculating the number of repeating times for each processor core to execute the parallel loop processing code other than processor cores necessary for executing a disturbance interrupting process when the disturbance interrupting process occurs during execution of the parallel loop processing code.

A computer-implemented method for controlling a plurality of processor cores implemented with a source code compiled by a compiler, the method comprising

• a parallel process of performing:
• a parallel loop process in which an internal processing operation is executed for a given number of repeating times and internal processing operations to be executed for the given number of repeating times are independent of each other and are parallelizable,
• calculating the number of processor cores which process the parallel processing code within the loop processing time on a basis of an operation clock, the operation power consumption corresponding to the frequency of the operation clock, and the loop processing time required to process the parallel loop processing code for each processor core for executing the parallel processing code, and defining a calculation result as a number of divided loops;
• selecting the processor core to be used on the basis of the number of divided loops, and calculating the operation clock for each of the selected processor cores;
• calculating a number of iteration times as the number of repeating times for each processor core used on a basis of the number of divided loops and a starting position of the iteration, and defining a calculation result as iteration information;
• control of dynamically changing a number of repeating times of the parallel loop processing performed by dividing the plurality of processor cores according to the received iteration information, and
• recalculating the number of repeating times for each processor core to execute the parallel loop processing code other than processor cores necessary for executing a disturbance interrupting process when the disturbance interrupting process occurs during execution of the parallel loop processing code.

A processor, comprising:

• a plurality of processor cores;
• and
• a control unit for each processor core for:
• calculating a number of processor cores which perform a process of a parallel processing code and for acquisition of a result as a number of divided loops;
• selecting the processor core used on a basis of the number of divided loops, and calculation of an operation clock for each selected processor core;
• calculating a number of iteration times as a number of repeating times for each processor core used on a basis of the number of divided loops and a starting position of the iteration, and for definition of a calculation result as iteration information;
• and
• calculating a necessary number of processor cores for performing processing within a loop processing, selecting the processor core on a basis of an operation clock, operation power consumption corresponding to a frequency of the operation clock, and a necessary loop processing time for parallel loop processing, and calculating the operation clock for each selected processor core, wherein
• when a disturbance interrupting process occurs during the parallel loop processing, a number of repeating times of an internal processing operation executed in a parallel loop processing code is calculated for each processor core to execute the parallel loop processing code other than processor cores necessary for executing the disturbance interrupting process.