Test path selection and test program generation for performance testing integrated circuit chips

A computer program product, comprising:

• a computer usable storage device having a computer readable program code embodied therein, said computer readable program code comprising an algorithm adapted to implement a method for test path selection and test program generation for performance testing integrated circuit chips, said method comprising the steps of:
• identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains performing a beginning of life timing simulation for all data paths;
• selecting, from said data paths, critical paths for each clock domain of the multiple clock domains, said critical paths being data paths between an input point and an output point wherein a time delay of a data signal presented at said input point and received at said output point must be between an upper performance specification and a lower performance specification;
• for each clock domain of said multiple clock domain, selecting the sensitizable paths of said critical paths;
• for each clock domain of said multiple clock domain, selecting test paths from the sensitizable critical paths generating process parameter values for each critical path, said selecting said test paths from said sensitizable critical paths based in part on said process parameter values;
• and
• creating a test program to performance test said test paths.