Constraint optimization of sub-net level routing in asic design

A computer program product for optimizing connection constraints in an integrated circuit (IC) design, the computer program product comprising:

• a non-transitory computer readable storage medium having computer usable program code embodied therewith, the computer usable program code configured to:
• determine a target timing path associated with a first of a plurality of sub-connections of the integrated circuit, wherein the first of the plurality of sub-connections is associated with a current connection constraint set;
• determine a timing probability value associated with the first of the plurality of sub-connections based, at least in part, on the target timing path associated with the first of the plurality of sub-connections, wherein the timing probability value indicates a probability that timing closure is satisfied on the target timing path associated with the first of the plurality of sub-connections;
• determine a route probability value associated with the first of the plurality of sub-connections based, at least in part, on the target timing path associated with the first of the plurality of sub-connections, wherein the route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion;
• identify a connection constraint model to which the first of the plurality of sub-connections corresponds based, at least in part, on the timing probability value associated with the first of the plurality of sub-connections and the route probability value associated with the first of the plurality of sub-connections;
• and
• modify the current connection constraint associated with the first of the plurality of sub-connections in accordance with the connection constraint model to which the first of the plurality of sub-connections corresponds.

An apparatus for optimizing connection constraints in an integrated circuit (IC) design comprising:

• a processor;
• a connection constraint optimization unit coupled with the processor, the connection constraint optimization unit operable to:
• determine a target timing path associated with a first of a plurality of sub-connections of the integrated circuit, wherein the first of the plurality of sub-connections is associated with a current connection constraint set;
• determine a timing probability value associated with the first of the plurality of sub-connections based, at least in part, on the target timing path associated with the first of the plurality of sub-connections, wherein the timing probability value indicates a probability that timing closure is satisfied on the target timing path associated with the first of the plurality of sub-connections;
• determine a route probability value associated with the first of the plurality of sub-connections based, at least in part, on the target timing path associated with the first of the plurality of sub-connections, wherein the route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion;
• identify a connection constraint model to which the first of the plurality of sub-connections corresponds based, at least in part, on the timing probability value associated with the first of the plurality of sub-connections and the route probability value associated with the first of the plurality of sub-connections;
• and
• modify the current connection constraint associated with the first of the plurality of sub-connections in accordance with the connection constraint model to which the first of the plurality of sub-connections corresponds.