Global leakage power optimization
AssigneeSynopsys, Inc.
InventorsMahesh A. Iyer, Sudipto Kundu
Life of this patent
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Abstract
Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.
Claims21
A computer-executed method for optimizing a circuit design's leakage power, the method comprising:
- determining leakage potentials for logic gates in the circuit design, wherein a logic gate's leakage potential is determined based on a difference between the logic gate's leakage power and a leakage power of another logic gate in a library;
- determining a processing order for processing the logic gates based at least on the leakage potentials;
- and
- optimizing, by computer, the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order, wherein said optimizing involves:
- selecting a leakage-power-reducing transformation to apply to one or more logic gates, and
- in response to determining that applying the selected leakage-power-reducing transformation to the one or more logic gates does not violate any design requirements in the circuit design, applying the selected leakage-power-reducing transformation to the one or more logic gates.
A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for optimizing a circuit design's leakage power, the method comprising:
- determining leakage potentials for logic gates in the circuit design, wherein a logic gate's leakage potential is determined based on a difference between the logic gate's leakage power and a leakage power of another logic gate in a library;
- determining a processing order for processing the logic gates based at least on the leakage potentials;
- and
- optimizing the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order, wherein said optimizing involves:
- selecting a leakage-power-reducing transformation to apply to one or more logic gates, and
- in response to determining that applying the selected leakage-power-reducing transformation to the one or more logic gates does not violate any design requirements in the circuit design, applying the selected leakage-power-reducing transformation to the one or more logic gates.
An apparatus for optimizing a circuit design's leakage power, comprising:
- a power-analysis mechanism configured to determine leakage potentials for logic gates in the circuit design, wherein a logic gate's leakage potential is determined based on the logic gate's leakage power and a leakage power of another logic gate in a library;
- a sorting mechanism configured to determine a processing order for processing the logic gates based at least on the leakage potentials;
- and
- a power-optimization mechanism configured to optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order, wherein said optimizing involves:
- selecting a leakage-power-reducing transformation to apply to one or more logic gates, and
- in response to determining that applying the selected leakage-power-reducing transformation to the one or more logic gates does not violate any design requirements in the circuit design, applying the selected leakage-power-reducing transformation to the one or more logic gates.
Dependencies are inferred from the claim text.