Bonding controller guided assessment and optimization for chip-to-chip stacking

A computer usable program product comprising a computer usable storage device including computer usable code for performance-based chip-to-chip stacking, the computer usable code comprising:

• computer usable code for selecting a first candidate chip from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit;
• computer usable code for activating a part of a 3D performance determinant in the first candidate chip;
• computer usable code for measuring a value of a performance parameter of the first candidate chip for a set of operating conditions;
• computer usable code for computing a stacked performance value for the first candidate chip using the value;
• and
• computer usable code for stacking a subset of the set of candidate chips in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.

A data processing system for performance-based chip-to-chip stacking, the data processing system comprising:

• a storage device including a storage medium, wherein the storage device stores computer usable program code;
• and
• a processor, wherein the processor executes the computer usable program code, and wherein the computer usable program code comprises:
• computer usable code for selecting a first candidate chip from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit;
• computer usable code for activating a part of a 3D performance determinant in the first candidate chip;
• computer usable code for measuring a value of a performance parameter of the first candidate chip for a set of operating conditions;
• computer usable code for computing a stacked performance value for the first candidate chip using the value;
• and
• computer usable code for stacking a subset of the set of candidate chips in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.