Semiconductor integrated circuit and pattern layouting method for the same

A pattern lay-outing method for lay-outing patterns of a semiconductor integrated circuit comprising functional areas formed within a chip and including scribing areas, module areas and an I/O area;

• and a dummy pattern formed in a space area within the chip, the space area being defined between the functional areas, within any of the functional areas, and/or at a position spanning an area where any of the functional areas is formed and an area formed with none of the functional areas, the dummy pattern including:
• a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern;
• a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion;
• and a plurality of non-forming areas positioned on the inner periphery side of the first metal portion in an area where the second metal portion is not formed, the pattern lay-outing method comprising the steps of:
• preparing reference plotting data defined by the functional areas formed within the chip;
• oversizing the reference plotting data by a predetermined width;
• subtracting the oversized reference plotting data from the chip to calculate the space area;
• forming island areas within the space area, the island areas having a shape corresponding to the non-forming areas;
• and
• subtracting the island areas from a space area positioned inside the outer edge of the dummy pattern to be formed.