Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs

A machine readable product for static timing analysis of an integrated circuit design, the machine readable product comprising:

• a non-transitory machine readable medium having machine readable program code stored therein including
• machine readable program code to automatically partition an integrated circuit design into a plurality of subcircuit stages;
• machine readable program code to automatically model each subcircuit stage of the integrated circuit design with a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network of at least one victim net and at least one aggressor net coupled together, wherein each subcircuit stage of the integrated circuit design includes a set of related edges of a design graph to compute signal propagation delay;
• and
• machine readable program code to automatically concurrently compute full timing delays for each edge of each subcircuit stage, including concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays for at least one glitch response to the at least one aggressor driver and the interconnect network.

A system for static timing analysis of an integrated circuit design, the system comprising:

• a processor to execute instructions to perform operations in analyzing timing of an integrated circuit design;
• and
• a storage device coupled to the processor, the storage device to store instructions that when executed by the processor cause the processor to perform operations including
• partitioning an integrated circuit design into a plurality of subcircuit stages;
• modeling each subcircuit stage of the integrated circuit design with a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network of at least one victim net and at least one aggressor net coupled together, wherein each subcircuit stage of the integrated circuit design includes a set of related edges of a design graph to compute signal propagation delay;
• and
• for each subcircuit stage, concurrently computing full timing delays for each edge of the design graph, including concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.