Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow

An electronic design automation tool including a model generator embodied as a series of operating instructions stored on a non-transitory computer-readable medium that are executed by a processor, the model generator comprising:

• a block analyzer configured to analyze design constraints and structures of a block of an integrated circuit to generate input and output timing constraints for said block;
• and
• an interface timing generator configured to combine said input and output timing constraints with clock customization data based on designer knowledge of said integrated circuit to generate interface timing parameters for said block;
• wherein the model generator provides a model of said block and wherein said model for said block includes:
• external points for both input and output clock signals;
• internal points injected between inputs and outputs of said external points, wherein said internal points:
• separate clock information from data information;
• and
• include at least two of:
• a delayed input clock;
• an internal clock;
• a generated clock;
• a delayed internal clock;
• and
• a delayed generated clock.

A non-transitory computer-readable medium having stored thereon instructions that, when executed, direct the operation of a processor to implement a method for designing an integrated circuit, said method comprising:

• generating an input and output timing budget for said block based on design constraints of said block and a netlist of said block;
• updating said input and output timing budget with clock customization data based on designer knowledge of said integrated circuit;
• and
• providing said model for said block based on said update of said input and output timing budget, wherein said model:
• represents clock information separately from data path information;
• includes external points for both input and output clock signals;
• and
• includes internal points injected between inputs and outputs of said external points, wherein said internal points:
• separate said clock information from said data information;
• and
• include at least two of:
• a delayed input clock;
• an internal clock;
• a generated clock;
• a delayed clock;
• and
• a delayed generated clock.