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US 8,543,949 B1Granted
Allocating hardware resources for high-level language code sequences
AssigneeAltera Corporation
InventorJeffrey Orion Pritchard
Life of this patent
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Abstract
Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences or subroutines provided in a high-level language are overloaded with information to specify the number of hardware resources such as logic elements or functional blocks used to implement the code on a programmable chip. Code sequences remain compliant with standard high-level language compilers while also being able to provide resource count information to high-level language to hardware compilers.
Claims20
A method comprising:
- receiving a code sequence from an input interface including a processor, along with a hardware resource count specifying a number of hardware resources that are to be allocated for the code sequence, in a high-level language program;
- generating hardware acceleration logic for implementing the code sequence using the number of hardware resources specified by the hardware resource count, wherein the number of hardware resources is associated with an amount of logic used to implement the code sequence on a programmable device;
- and
- implementing the hardware acceleration logic on the programmable device.
1 more element
A system comprising:
- an input interface operable to receive a code sequence, along with a hardware resource count specifying a number of hardware resources that are to be allocated for the code sequence, in a high-level language program, wherein the interface includes a processor;
- and
- a processor operable to generate hardware acceleration logic for implementing the code sequence using the number of hardware resources specified by the hardware resource count, wherein the number of hardware resources is associated with an amount of logic used to implement the code sequence on a device;
- wherein the hardware acceleration logic is implemented on the device.
1 more element
A non-transitory computer readable storage medium comprising:
- computer code for receiving a code sequence from an input interface including a processor, along with a hardware resource count specifying a number of hardware resources that are to be allocated for the code sequence, in a high-level language program;
- computer code for generating hardware acceleration logic for implementing the code sequence using the number of hardware resources specified by the hardware resource count, wherein the number of hardware resources is associated with an amount of logic used to implement the code sequence on a device;
- and
- computer code for implementing the hardware acceleration logic on the device.
1 more element
Dependencies are inferred from the claim text.