Power-optimized decoding of linear codes
AssigneeApple Inc.
InventorsMicha Anholt, Naftali Sommer
Life of this patent
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Abstract
A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.
Claims24
A method, comprising:
- accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder;
- pre-processing the input code word to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word;
- decoding the pre-processed code word using the ECC decoder;
- and
- recovering the data from the decoded pre-processed code word;
- wherein pre-processing the input code word comprises replacing the input code word with an all-zeros code word, and wherein decoding the pre-processed code word comprises causing the ECC decoder to converge to an error pattern in the input code word.
An apparatus, comprising:
- a hardware-implemented Error Correction Code (ECC) decoder, which is configured to decode ECC code words;
- and
- ancillary circuitry, which is configured to accept an input code word, which was produced by encoding data with the ECC, to pre-process the input code word to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word, to decode the pre-processed code word using the ECC decoder, and to recover the data from the decoded pre-processed code word;
- wherein the ancillary circuitry is configured to replace the input code word with an all-zeros code word, to provide the all-zeros code word as input to the ECC decoder, and to cause the ECC decoder to converge to an error pattern in the input code word.
Dependencies are inferred from the claim text.