US 8,543,876 B1 · Method and apparatus for serial scan test data delivery

Abstract

A design for test (DFT) circuitry which delivers serial data serially is disclosed. The DFT circuit has a transceiver to receive serial data and then deserialize the serial data into deserialize data. The DFT circuit also has a control logic block which receives the deserialize data and stimulates at least one test element with the test data. The test element will generate an output response from the stimulus. The DFT circuit also has an output response block which receives the output from the test element and analyses the output response. Utilizing this DFT circuitry, a high speed data delivery method can be used for testing a device-under-test (DUT). Such method could reduce test time and the test cost associated with test process.

Claims18

Dependent claims

An integrated circuit (IC) comprising:

a transceiver block which receives serial data and converts the serial data to deserialized data;
a control logic block which receives the deserialized data from the transceiver block and generates stimulus for testing the IC, wherein the control logic block includes a control block, a scan register, and a programming register;
a core fabric which receives the stimulus from the control logic block and propagates the stimulus through the core fabric based on clock cycles through a shift register;
and
an output response block for receiving output from the core fabric, wherein the control logic block further includes a Capture RAM to store information contained within the scan register and the output response block from the core fabric.

2 more elements

Dependencies are inferred from the claim text.

Method and apparatus for serial scan test data delivery

Life of this patent

Method and apparatus for serial scan test data delivery

Life of this patent

Abstract

Claims18