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US 8,543,874 B2Granted
Macro and command execution from memory array
AssigneeMicron Technology, Inc.
InventorsFrankie F. Roohparvar, Benjamin Louie
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device. Decode blocks adapted to interpret instructions and data stored in the memory device. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.
Claims22
A method of testing a memory device comprising:
- performing a read operation of a location of a first plurality of memory cells of the memory device in response to a first received command;
- decoding data read from the first plurality of memory cells into a first test program for testing a second plurality of memory cells of the memory device;
- and
- testing the second plurality of memory cells utilizing the first test program;
- wherein decoding data read from the first plurality of memory cells into the first test program comprises decoding from the data read from the first plurality of memory cells at least one of a macro, a command, and an instruction for control circuitry of the memory device to perform the testing of the second plurality of memory cells.
2 more elements
A method of testing a memory device comprising:
- storing data corresponding to a first test program in a location of a first plurality of memory cells of the memory device;
- performing a read operation of the data corresponding to the first test program stored in the location of the first plurality of memory cells in response to a first received command;
- decoding data read from the first plurality of memory cells into the first test program for testing a second plurality of memory cells of the memory device;
- and
- testing the second plurality of memory cells utilizing the first test program;
- wherein decoding data read from the first plurality of memory cells into the first test program comprises decoding from the data read from the first plurality of memory cells at least one of a macro, a command, and an instruction for control circuitry of the memory device to perform the testing of the second plurality of memory cells.
3 more elements
A method of testing a memory device comprising:
- performing a read operation of a location of a first plurality of memory cells of the memory device in response to a first received command, where memory cells of the location of the first plurality of memory cells are configured to operate as single level memory cells;
- decoding data read from the first plurality of memory cells into a first test program for testing a second plurality of memory cells of the memory device;
- and
- testing the second plurality of memory cells utilizing the first test program;
- wherein decoding data read from the first plurality of memory cells into the first test program comprises decoding from the data read from the first plurality of memory cells at least one of a macro, a command, and an instruction for control circuitry of the memory device to perform the testing of the second plurality of memory cells.
2 more elements
Dependencies are inferred from the claim text.