Multi-site testing of computer memory devices and serial IO ports

A memory device comprising:

• one or more memory banks for storage of data;
• an output including a serializer to serialize data;
• an input including a deserializer to deserialize data;
• a test generator to generate one or more test patterns for testing of the memory;
• an error detector to detect errors in received data;
• a switch and port logic coupled with the memory bank;
• and
• one or more switching elements to establish one or more test paths for the memory device, the test paths including a first test path for a first test mode and a second test path for a second test mode, wherein the first test path is a test path for a serial IO (input-output) test mode and the second test path is a test path for a memory interface test mode:
• wherein the serial IO test mode is separated from the memory interface test mode;
• and
• wherein test patterns generated for the memory interface test mode are limited to test patterns that are authorized for the memory interface test mode, and wherein test patterns generated by the test generator for the serial IO test mode include test patterns that are not authorized for the memory interface test mode.

A memory testing apparatus comprising:

• an input to receive data from one or more memory devices of a plurality of memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices;
• and
• an error checker to check the data from the one or more memory devices for errors, the error checker having a first test mode for testing a first aspect for the plurality of memory devices and a second test mode for testing a second aspect of the plurality of memory devices, wherein the first test mode is a serial IO (input-output) test mode and the second test mode is a memory interface test mode;
• wherein the serial IO test mode is separated from the memory interface test mode;
• and
• wherein test patterns generated for the memory interface test mode are limited to test patterns that are authorized for the memory interface test mode, and wherein test patterns generated by a test generator for the serial IO test mode include test patterns that are not authorized for the memory interface test mode.

A computer-readable non-transitory medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:

• coupling a plurality of memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices;
• generating test signal patterns using a test generator of each memory device;
• and
• serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the plurality of memory devices, wherein testing of the memory devices includes a first test mode and a second test mode;
• wherein the first test mode is a serial IO (input-output) test mode and the second test mode is a memory interface test mode;
• wherein the serial IO test mode is separated from the memory interface test mode;
• and
• wherein test patterns generated for the memory interface test mode are limited to test patterns that are authorized for the memory interface test mode, and wherein test patterns generated for the serial IO test mode include test patterns that are not authorized for the memory interface test mode.