Multi-core clocking system with interlocked ‘anti-freeze’ mechanism

Abstract

A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

Dependencies are inferred from the claim text.