Virtual core management
AssigneesSun Microsystems, Inc., Sun Microsystems Technology Ltd.
InventorsYu Qing Cheng, John Gregory Favor, Peter N. Glaskowsky, Carlos Puchol, Seungyoon Peter Song
Life of this patent
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Abstract
A virtual core management system including one or more physical cores, a virtual core including a collection of logical states associated with the execution of a program, and a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations.
Claims20
A system adapted for use with a computer processor having a bus unit and one or more physical processor cores, the system comprising:
- a memory component adapted to store one or more virtual cores;
- and
- a virtual core management component adapted to map the one or more virtual cores to at least one of the physical cores to enable an execution of one or more programs,
- wherein the virtual core management component is configured to unmap one or more virtual cores from one or more physical cores in response to one or more virtual cores being put into a sleep state,
- wherein the one or more virtual cores include one or more logical states associated with the execution of the one or more programs,
- wherein the mapping comprises transferring the one or more logical states of the one or more virtual cores from the memory component to the at least one physical core, and wherein the virtual core management component comprises a transaction redirection component adapted to route signals between the one or more physical cores and the bus unit based on the mapping of the virtual core.
A virtual core management system comprising:
- one or more physical cores;
- a virtual core including a collection of logical states associated with the execution of a program;
- and
- a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations,
- wherein the virtual core management component is configured to unmap the virtual core from a physical core in response to the virtual core being put into a sleep state, and
- wherein the virtual core management component comprises a transaction redirection component adapted to route signals between the one or more physical cores and a bus unit based on the mapping of the virtual core.
A method for use in a processing system comprising:
- providing one or more physical cores and a virtual core, the virtual core including a collection of logical states associated with the execution of a program;
- mapping the virtual core to at least one of the one or more physical cores based upon power management considerations;
- unmapping the virtual core from a physical core in response to the virtual core being put into a sleep state;
- and
- routing signals between the one or more physical cores and a bus unit based on the mapping of the virtual core using a transaction redirection component.
A non-transitory computer-readable medium that includes a circuit description of a virtual core management system, wherein the circuit description when interpreted by a computer system specifies the virtual core management system comprising:
- one or more physical cores;
- a virtual core including a collection of logical states associated with the execution of a program;
- and
- a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations,
- wherein the virtual core management component is configured to unmap the virtual core from a physical core in response to the virtual core being put into a sleep state, and
- wherein the virtual core management component comprises a transaction redirection component adapted to route signals between the one or more physical cores and a bus unit based on the mapping of the virtual core.
Dependencies are inferred from the claim text.