Memory access techniques including coalesing page table entries
AssigneeNVIDIA Corporation
InventorsDavid B. Glasco, Lingfeng Yuan
Life of this patent
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Abstract
A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced mappings are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can cache a single coalesced mapping and not all of them. The single cached coalesced mapping may be used to translate all of the virtual addresses to physical addresses for the corresponding contiguous memory space.
Claims17
A computing device comprising:
- a computing device-readable medium to store an address translation data structure;
- and
- a memory management unit, communicatively coupled to the computing device-readable medium, including:
- a cache to store one or more address mappings of the address translation data structure;
- and
- a paging module, communicatively coupled to the cache, to coalesce a plurality of address mappings stored in the address translation data structure between a virtual memory space and a physical memory space when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages, wherein;
- a first bit of a contiguous attribute, associated with a coalesced mapping, specifies a type of encoding;
- a plurality of other bits of the contiguous attribute specifies an actual number of contiguous pages when the first bit is set to a first state;
- and
- the plurality of other bits of the contiguous attribute specifies a power of two representation of the number of contiguous pages when the first bit is set to a second state.
A method of generating an address translation data structure comprising:
- determining if a plurality of contiguous pages in a virtual address space are mapped to a plurality of contiguous pages in a physical address space;
- generating a mapping between a virtual address and a corresponding physical address for each non-contiguous page and setting a contiguous attribute in the mapping to indicate that the mapping is not part of a set of contiguous pages;
- and
- generating a mapping for each contiguous virtual address and a corresponding contiguous physical address containing a page frame address of a given contiguous page and setting the contiguous attribute in the mapping to indicate that there are a plurality of contiguous pages, wherein;
- a first bit of the contiguous attribute specifies a type of encoding;
- a plurality of other bits of the contiguous attribute specifies an actual number of contiguous pages when the first bit is set to a first state;
- and
- the plurality of other bits of the contiguous attribute specifies a power of two representation of the number of contiguous pages when the first bit is set to a second state.
A method of accessing memory comprising:
- receiving a memory access request that includes a virtual address;
- determining if a valid non-coalesced mapping between the virtual address and a physical address is cached in a translation lookaside buffer;
- determining if a valid coalesced mapping between the virtual address in the memory access request and a physical address is cached in a translation lookaside buffer, wherein;
- a first bit of a contiguous attribute in the mapping specifies a type of encoding;
- a plurality of other bits of the contiguous attribute specifies an actual number of contiguous pages when the first bit is set to a first state;
- and
- the plurality of other bits of the contiguous attribute specifies a power of two representation of the number of contiguous pages when the first bit is set to a second state;
- and
- calculating a physical address as a function of a physical address and a virtual address in the mapping and the virtual address in the memory access request if a valid coalesced mapping is cached.
Dependencies are inferred from the claim text.