Method for maintaining cache coherence using a distributed directory with event driven updates
AssigneeSawyer Law Group, P.C.
InventorDavid Vernon James
Life of this patent
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Abstract
The present invention is a protocol for maintaining cache consistency between multiprocessors within a tightly coupled system. A distributed directory is maintained within the data-sharing processors, so that copies can be invalidated when modified. All transfers are event driven, rather the polled, to reduce bus-bandwidth consumption. Deadlocks are avoided by placing to-be-executed command codes in the returned response packets, when the request-forwarding queues are full or not present.
Claims10
A method for maintaining cache coherence using a distributed directory with event driven updates, the method comprising:
- providing a plurality of cache-coherent multiprocessors, wherein the plurality of cache-coherent multiprocessors are connected via a system interconnect, wherein the system interconnect only supports directed request and response packet deliveries;
- ensuring successful forwarding of a response packet is not dependent on any concurrently-active request packet;
- providing a set of stable coherent cache states and a set of unstable coherent cache states for the plurality of cache-coherent multiprocessors;
- in response to shared accesses attempting to access a previously modified cache-line address, converting a memory state from modified to shared by utilizing a washing technique;
- avoiding the washing technique on any of infrequent read-only and mixed read/write accesses;
- and
- avoiding deadlocks by placing to-be-executed command codes in returned response packets when request-forwarding queues are any of full and not present.
A system for maintaining cache coherence using a distributed directory with event driven updates, the system comprising a plurality of cache-coherent multiprocessors, wherein the plurality of cache-coherent multiprocessors are connected via a system interconnect, wherein the system interconnect only supports directed request and response packet deliveries, and a memory device coupled to the plurality of cache-coherent multiprocessors, wherein the memory device includes an application which, when executed by the plurality of cache-coherent multiprocessors, carries out the steps of:
- ensuring successful forwarding of a response packet is not dependent on any concurrently-active request packet;
- providing a set of stable coherent cache states and a set of unstable coherent cache states for the plurality of cache-coherent multiprocessors;
- in response to shared accesses attempting to access a previously modified cache-line address, converting a memory state from modified to shared by utilizing a washing technique;
- avoiding the washing technique on any of infrequent read-only and mixed read/write accesses;
- and
- avoiding deadlocks by placing to-be-executed command codes in returned response packets when request-forwarding queues are any of full and not present.
Dependencies are inferred from the claim text.