Efficient data prefetching in the presence of load hits

A memory subsystem in a microprocessor, comprising:

• a first-level cache;
• a second-level cache;
• and
• a prefetch cache, configured to speculatively prefetch cache lines from a memory external to the microprocessor;
• wherein the second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both;
• wherein if a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache.

A computer program product encoded in at least one non-transitory, tangible computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a memory subsystem in a microprocessor, the computer readable program code comprising:
• first program code for specifying a first-level cache;
• second program code for specifying a second-level cache;
• and
• third program code for specifying a prefetch cache, configured to speculatively prefetch cache lines from a memory external to the microprocessor;
• wherein the second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both;
• wherein if a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache.