US 8,543,754 B2 · Low latency precedence ordering in a PCI express multiple root I/O virtualization environment

Abstract

An apparatus and method of low latency precedence ordering check in a PCI Express (PCIe) multiple root I/O virtualization (MR-IOV) environment. The precedence ordering check mechanism aids in enabling a port to comply with PCIe MR-IOV ordering rules. A posted information array mirrors a posted transaction queue, storing precedence order indicator and Virtual Hierarchy (VH) tag information for corresponding posted transaction entries stored in the posted transaction queue. The selector queries the posted information array periodically, such as each cycle, to determine whether the non-posted/completion transaction at the output of their respective queues have any preceding posted transactions of the same VH somewhere in the posted queue.

Claims24

Dependent claims

An apparatus for precedence ordering for use in a PCIe multiple root I/O virtualization (MR-IOV) environment, comprising:

a posted information array operative to store only essential ordering information extracted from and associated with posted transactions data in a corresponding posted transaction queue, said essential ordering information including those portions of posted transactions data necessary for ordering;
and
a precedence ordering check circuit operative to enforce PCIe MR-IOV Virtual Hierarchy (VH) ordering rules by determining, in accordance with the contents of said posted information array, whether or not there is a transaction in the posted queue from the same VH that preceded a current non-posted/completion transaction.

Dependencies are inferred from the claim text.

Low latency precedence ordering in a PCI express multiple root I/O virtualization environment

Life of this patent

Low latency precedence ordering in a PCI express multiple root I/O virtualization environment

Life of this patent

Abstract

Claims24