Apparatus and method for increased address range of an I2C or I2C compatible bus

A method for operating an integrated circuit (IC) as an inter-integrated circuit (I2C) slave connected to a master on an I2C bus, the method comprising:

• receiving at the IC an address issued by a master onto an I2C bus, wherein the IC includes a data-in terminal, a clock-in terminal, a data-out terminal, a clock-out terminal, a first register, a second register, a acknowledge circuit, and a logic circuit;
• temporarily storing the address into the first register;
• detecting by the IC whether another slave on the I2C bus has acknowledged the address;
• generating by the acknowledge circuit a not-acknowledge signal when no other slave has acknowledged the address as its address;
• receiving by the logic circuit, the not-acknowledge signal generated by the acknowledge circuit;
• receiving and storing the address from the first register in the second register when no other slave has acknowledged the address;
• and
• acknowledging that the address corresponds to the IC when the address is stored in the second register.

An apparatus comprising:

• I2C bus having a data line and a clock line;
• a master that is coupled to the I2C bus;
• and
• a plurality of slaves that are each coupled to the I2C bus, wherein at least one slave includes:
• a data-in terminal that is coupled to the data line;
• a clock-in terminal that is coupled to the clock line;
• a data-out terminal that is coupled to the data line;
• a clock-out terminal that is coupled to the clock line;
• a first register that is coupled to the data-in terminal and the clock-in terminal, wherein the first register stores an address transmitted by the master over the I2C bus;
• an acknowledge circuit that is coupled to the data-in terminal and the clock-in terminal, wherein the acknowledge circuit is configured to generate a not-acknowledge signal when no other slave has acknowledged the address as its address;
• a logic circuit that is coupled to the acknowledge circuit, wherein the logic circuits receives the generated not-acknowledge signal;
• and
• a second register that is coupled to the logic circuit and the first register, wherein the second register is configured to receive the address from the first register when the acknowledge circuit generates the not-acknowledge signal and the slave is configured to be identified by the address when the address is stored in the second register.