Phase adjustment apparatus and method for a memory device signaling system

A method, performed by an integrated circuit device, the method comprising:

• generating a plurality of phase vector clock signals;
• generating a receiver clock with a phase determined in accordance with a combination of a set of at least two phase vector clock signals of the plurality of phase vector clock signals;
• generating a transmit clock with a phase determined in accordance with a combination of a set of at least two phase vector clock signals of the plurality of phase vector clock signals;
• receiving receive data with receive timing in accordance with the phase of the receiver clock;
• transmitting transmit data with transmit timing in accordance with the phase of the transmit clock.

An integrated circuit device comprising:

• a clock generator circuit to generate a plurality of phase vector clock signals;
• a first circuit to generate a receiver clock with a phase that is interpolated from a first set of phase vector clock signals of the plurality of phase vector clock signals;
• a second circuit to generate a transmit clock with a phase that is interpolated from a second set of phase vector clock signals of the plurality of phase vector clock signals;
• an input sampling circuit configured to time receiving of receive data in accordance with the phase of the receiver clock;
• and
• an output circuit configured to time transmission of transmit data in accordance with the phase of the transmit clock.

A method, performed by an integrated circuit device, the method comprising:

• generating a plurality of phase vector clock signals;
• interpolating between a first set of the phase vector clock signals to generate a receiver clock;
• interpolating between a second set of the phase vector clock signals to generate a transmit clock;
• receiving receive data with receive timing in accordance with a phase of the receiver clock;
• transmitting transmit data with transmit timing in accordance with a phase of the transmit clock.