Multi-channel sample rate converter
AssigneeEvertz Microsystems Ltd.
InventorJeff Wei
Life of this patent
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Abstract
A method of sample rate conversion and clock synchronization for multiple asynchronous input signals using a single processing core. A sample processing clock with a frequency equal to or higher than the input signal clock frequencies is provided. The clock period is divided into a number of time slots corresponding to the input signals. For each valid sample of an input signal, the core performs a first stage processing operation on the sample. Subsequently, for each required sample of an output signal, the core performs a second stage processing operation to generate the output sample.
Claims8
A method of sample rate conversion for at least one input signal, each at least one input signal having a plurality of input samples, comprising:
- receiving the at least one input signal;
- generating an intermediate signal with an intermediate clock rate that is higher than or equal to each at least one input signal;
- providing N channels in the intermediate signal, wherein N is an integer value corresponding to the number of input signals, and wherein each of the N channels corresponds to one and only one input signal;
- for each at least one input signal, processing each of the plurality of input samples in the at least one input signal to produce a plurality of intermediate samples for the corresponding channel;
- providing an output reference clock signal;
- and
- generating N output signals synchronized to the output reference clock signal, each output signal corresponding to one channel in the intermediate signal, wherein each output signal is generated by filtering the plurality of intermediate samples corresponding to each channel to produce a plurality of output samples in the corresponding output signal,
- wherein the at least one input signal comprises a plurality of input signals, and wherein the N channels in the intermediate signal are provided by multiplexing the intermediate signal to accommodate the plurality of input signals, and wherein the multiplexing comprises dividing each clock period of the intermediate signal into N time slots.
Dependencies are inferred from the claim text.