Receiver architecture and methods for demodulating binary phase shift keying signals

A receiver comprising:

• a first injection-locked oscillator (ILO) having a first input configured to receive a binary phase shift keying (“BPSK”) signal, a first ILO variable capacitor to change a resonant frequency of the first ILO, and a second input configured to receive a first control input for controlling the first ILO variable capacitor;
• a second injection-locked oscillator (ILO) having a third input configured to receive said BPSK signal, a second ILO variable capacitor to change a resonant frequency of the second ILO, and a fourth input configured to receive a second control input for controlling the second ILO variable capacitor;
• a digital control logic circuit having a channel selection input, a first ILO control circuit and a second ILO control circuit;
• the first ILO control circuit coupled with said second input of said first ILO, said first ILO control circuit configured to generate said first control input;
• and
• the second ILO control circuit coupled with said fourth input of said second ILO, said second ILO control circuit configured to generate said second control input;
• and,
• the first ILO control circuit configured to adjust the resonant frequency of the first ILO by a positive frequency offset and the second ILO control circuit configured to adjust the resonant frequency of the second ILO by a negative frequency offset, where the positive frequency offset and the negative frequency offset are determined according to a data rate of the BPSK signal.

A method for demodulating comprising:

• receiving a channel selection input signal;
• tuning a receiver to a selected channel by controlling a resonant frequency of a first injection-locked oscillator (ILO) to a frequency above one half of a carrier frequency of the selected channel, and controlling a resonant frequency of a second injection-locked oscillator (ILO) to a frequency below one half of the carrier frequency of the selected channel;
• receiving a binary phase shift keyed signal;
• generating a first channel based on said binary phase shift keyed signal;
• generating a second channel based on said binary phase shift keyed signal;
• processing said first channel using a first circuit including the first ILO coupled with a first ILO control circuit to generate a first output;
• processing said second channel using a second circuit including a second ILO coupled with a second ILO control circuit to generate a second output;
• and
• multiplying said first output with said second output.

A receiver comprising:

• a first injection-locked oscillator (ILO) having a first input configured to receive a binary phase shift keying (“BPSK”) signal and a second input configured to receive a first ILO resonant frequency control signal;
• a second injection-locked oscillator (ILO) having a third input configured to receive said BPSK signal and a fourth input configured to receive a second ILO resonant frequency control signal;
• a first control logic circuit coupled with said second input of said first ILO, said first control logic circuit configured to generate said first ILO resonant frequency control signal;
• and
• a second control logic circuit coupled with said fourth input of said second ILO, said second control logic circuit configured to generate said second ILO resonant frequency control signal;
• and,
• an amplifier having a positive output and a negative output, said positive output coupled with said first ILO and said negative output coupled with said second ILO.