Power and area efficient SerDes transmitter

A transmitter comprising:

• a digital block operating in a digital voltage domain, the digital block comprising:
• a first storage element to store a first group of bits;
• a second storage element to receive from the first storage element a second group of bits;
• and
• an analog block operating in an analog voltage domain, the analog block comprising:
• phase alignment circuitry to receive the first group of bits from the first storage element and the second group of bits from the second storage element, wherein a width of a datapath between the first and second storage elements and the phase alignment circuitry is equal to a total number of bits in the first and second groups of bits;
• and
• an output driver comprising a plurality of staging flops, the output driver configured to receive different combinations of bits from the first and second groups of bits,
• wherein the different combinations of bits comprises one or more bits from the first group of bits and zero or more bits from the second group of bits.

A method comprising:

• receiving a first group of bits of parallel data in a digital block;
• storing history bits in the digital block;
• transferring the first group of bits and the history bits from the digital block to an analog block;
• generating in the analog block a plurality of combinations of bits, each combination comprising one or more bits from the first group of bits and zero or more bits from the history bits;
• aligning a first combination from the plurality of combinations of bits to a phase of a clock;
• and
• inputting the first combination into an output driver to produce an output signal.

A system comprising:

• a first electronic component comprising a receiver;
• a connector;
• a second electronic component comprising a transmitter configured to transmit data to the first electronic component via the connector, the transmitter comprising:
• a digital block operating in a digital voltage domain, the digital block comprising:
• a first storage element to store a first group of bits of data in parallel;
• and
• a second storage element to store history bits from another group of data;
• and
• an analog block operating in an analog voltage domain, the analog block comprising:
• circuitry to receive the first group of bits of data from the digital block;
• circuitry to receive the history bits from the digital block;
• circuitry to generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits;
• phase alignment circuitry to align each combination of bits to a phase of a clock;
• and
• an output driver to produce an output signal in response to receiving each combination.