Methods and apparatus for providing a scalable deblocking filtering assist function within an array processor

A method for scalable block pixel filtering comprising:

• issuing a block filtering instruction to a plurality of processing elements (PEs) to initiate block pixel filtering operations in parallel on a plurality of hardware assist units (HAUs) and a plurality of memory units, each PE coupled to an HAU associated with that PE and separately coupled to a memory unit associated with that PE and each associated HAU separately coupled to the associated memory unit, by causing at least one command and at least one parameter be sent from each PE to the associated HAU;
• fetching a block of pixels in parallel from each memory unit to be stored in a register file within each associated HAU;
• processing in each associated HAU a subset of the block of pixels to generate sub-block parameters;
• and
• filtering in each associated HAU the stored block of pixels in a horizontal and vertical edge filtering computation pipeline using the sub-block parameters, wherein each associated HAU utilizes boundary strength (Bs) value for a block boundary between two neighboring pixel blocks to select a computation data path to perform edge filtering.

A method for block filtering comprising:

• fetching a block of pixels from a processing element (PE) memory to a register file within a hardware assist unit (HAU);
• filtering vertical edges of the block of pixels accessed from the register file in a HAU computational pipeline to produce a vertically filtered block of pixels, wherein the HAU utilizes a boundary strength (Bs) value for each block boundary between two neighboring pixel blocks to select a computation data path to perform vertical edge filtering;
• storing the vertically filtered block of pixels in a byte addressable memory within the HAU;
• fetching in transposed order the vertically filtered block of pixels by use of transpose addresses from the byte addressable memory into the register file as a transposed filtered block of pixels;
• filtering horizontal edges of the transposed filtered block of pixels accessed from the register file in the HAU computational pipeline to produce a vertically and horizontally filtered block of pixels, wherein the HAU utilizes a boundary strength (Bs) value for each block boundary between two neighboring pixel blocks to select a computation data path to perform horizontal edge filtering;
• and
• storing the vertically and horizontally filtered block of pixels in the PE memory.

A method for block filtering comprising:

• fetching a first block of pixels from a first memory to a first register file within a first hardware assist unit (HAU) in parallel with fetching a second block of pixels from a second memory to a second register file within a second HAU;
• filtering vertical edges of the first block of pixels accessed from the first register file to produce a first filtered block of pixels in parallel with filtering vertical edges of the second block of pixels accessed from the second register file to produce a second filtered block of pixels, wherein each HAU separately utilizes a boundary strength (Bs) value for each block boundary between two neighboring pixel blocks to select a computation data path to perform vertical edge filtering in each HAU;
• storing the first filtered block of pixels in a first byte addressable memory within the first HAU in parallel with storing the second filtered block of pixels in a second byte addressable memory within the second HAU;
• fetching the first filtered blocks of pixels in transposed order from the first byte addressable memory into the first register file as a first transposed block of pixels in parallel with fetching the second filtered block of pixels in transposed order from the second byte addressable memory into the second register file as a second transposed block of pixels;
• filtering horizontal edges of the first transposed block of pixels accessed from the first register file to produce a third filtered block of pixels in parallel with filtering horizontal edges of the second transposed block of pixels accessed from the second register file to produce a fourth filtered block of pixels, wherein each HAU separately utilizes a boundary strength (Bs) value for each block boundary between two neighboring pixel blocks to select a computation data path to perform horizontal edge filtering in each HAU;
• and
• storing the third filtered blocks of pixels in the first memory in parallel with storing the fourth filtered block of pixels in the second memory.