Managing free packet descriptors in packet-based communications

A method of localized managing of communication packets in a network element, each packet having a data packet and an associated packet descriptor, by way of a free packet descriptor queue, the method comprising the steps of:

• identifying a packet descriptor that is not associated with an active packet queue, the packet descriptor associated with a pointer to a memory location at which the packet descriptor is located in the memory;
• determining whether the identified packet descriptor is located in a first memory resource or in a second memory resource of the memory, the second memory resource having slower access performance than the first memory resource;
• responsive to the identified packet descriptor being located in the first memory resource, updating a head packet descriptor index field in a free packet descriptor queue control register associated with the free packet descriptor queue to refer to the packet descriptor to be added;
• and
• responsive to the identified packet descriptor being located in the second memory resource, updating a tail packet descriptor field in the free packet descriptor queue control register to refer to the packet descriptor to be added.

A network element, comprising:

• network interface circuitry on an integrated circuit for coupling to a network;
• an addressable memory for storing packet descriptors and data packets, each data packet associated with one of the packet descriptors, the addressable memory comprising:
• an on-chip first memory resource realized in the integrated circuit and having memory locations within a system memory space;
• and
• a second memory resource, the second memory resource having slower access performance relative to the processor than the first memory resource and external to the integrated circuit;
• linking memory, realized in the on-chip memory, coupled to the queue manager, and having a plurality of entries, each entry mapped to one of a plurality of packet descriptor index values, each packet descriptor index value mapped to a memory address in the addressable memory, and each entry of the linking memory having a field for storing a next packet descriptor index value;
• and
• a processor, coupled to the network interface circuitry and to the random access memory, the processor realized in an integrated circuit and comprising:
• a queue manager, for localizing linking, coupled to the first memory resource and the second memory resource, comprising:
• queue manager logic circuitry;
• and
• a free packet descriptor queue control register;
• wherein the queue manager keeps base queue information in the first memory resource and adds a packet descriptor to a free packet descriptor queue associated with the free packet descriptor queue control register by performing a sequence of operations comprising:
• receiving a return request including a pointer to the location in memory of the packet descriptor to be added;
• determining whether the packet descriptor is located in the first memory resource or the second memory resource;
• responsive to the packet descriptor being located in the first memory resource, updating a head packet descriptor field in the free packet descriptor queue control register to refer to the packet descriptor to be added;
• and
• responsive to the packet descriptor being located in the second memory resource, updating a tail packet descriptor field in the free packet descriptor queue control register to refer to the packet descriptor to be added.