DLL circuit, frequency-multiplication circuit, and semiconductor memory device

A frequency-multiplication circuit, comprising:

• a delay chain in which delay elements are connected in series having a plurality of stages numbered from 1 to N (N a positive integer) that generate delay clocks having mutually different delay amounts with respect to a reference clock;
• a plurality of phase comparators that receives the reference clock, and receives clocks from delay elements that are in a different stage among the plurality of stages of the delay elements;
• a controller that simultaneously receives comparison results from the plurality of phase comparators, determines the stage number that generates the clock of which a phase is synchronized with a phase of the reference clock from among the plurality of stages of the delay elements, and selects a stage from among the plurality of stages of the delay elements based on the determined stage number so that delay clocks among the said delay clocks, each having a demanded delay amount with respect to the reference clock, are output;
• and
• a generating unit that receives the reference clock, receives the delay clocks output by the controller, and generates and outputs a multiplication clock obtained by multiplying the reference clock.

A semiconductor memory device comprising:

• a DLL circuit that delays a reference clock to generate a delay clock, and outputs the delay clock;
• and
• memory that operates by the output delay clock,
• wherein the DLL circuit includes:
• a delay chain in which delay elements are connected in series having a plurality of stages numbered from 1 to N (N a positive integer) that generate delay clocks having mutually different delay amounts with respect to the reference clock;
• a plurality of phase comparators, each receiving the reference clock individually and each receiving respectively a clock from a corresponding stage of the delay elements, wherein the clocks received by the comparators from the delay elements are from mutually different stages among the plurality of stages of the delay elements;
• and
• a controller that simultaneously receives comparison results from the plurality of phase comparators, determines the stage number that generates the clock of which a phase is synchronized with a phase of the reference clock from among the plurality of stages of the delay elements, and selects a stage from among the plurality of stages of the delay elements based on the determined stage number so that a delay clock among said delay clocks having a demanded delay amount with respect to the reference clock is output.