Circuit and method for reducing leakage current
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorDariusz Kowalczyk
Life of this patent
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Abstract
A circuit comprises a first voltage source, a second voltage source, a first switch, firsts transistors, and a control circuitry. The first switch is configured to selectively couple the first voltage source or the second voltage source to a first signal line. The first transistors are in an IO circuitry and have first bulks configured to receive the first signal line. The control circuitry is configured to receive a clock and a command signal on a command signal line, and generate a first control signal on a first control signal line to control the first switch based on the clock and the command signal.
Claims20
A circuit comprising:
- a first voltage source and a second voltage source;
- a first switching circuit configured to selectively couple the first voltage source or the second voltage source to a first signal line;
- first transistors in an IO circuitry having first bulks configured to receive the first signal line;
- and
- a control circuitry configured to receive a clock and a command signal on a command signal line and generate a first control signal on a first control signal line to control the first switching circuit based on the clock and the command signal.
A method for reducing leakage current in a memory macro, comprising:
- changing from a first operational mode to a second operational mode of the memory macro;
- changing a first voltage value at first bulks of transistors of an input/output circuitry of the memory macro to a second voltage value;
- and
- maintaining the first voltage value at bulks of transistors of a memory circuitry of the memory macro,
- wherein
- the IO circuitry carries first data for a write operation to memory cells in the memory circuitry and second data for a read operation from the memory cells in the memory circuitry;
- and
- the first operational mode includes at least one of the read operation and the write operation, and the second operational mode prohibits the read operation and the write operation.
A memory circuit comprising:
- a first voltage source and a second voltage source;
- a first switching circuit configured to selectively couple the first voltage source or the second voltage source to a first signal line;
- first transistors in an IO circuitry having first bulks configured to receive the first signal line,
- wherein
- the circuit is configured to operate in a first operational mode and in at least one of a second operational mode, a third operational mode or a fourth operational mode;
- in the first operational mode, the circuit is configured to have a read operation or a write operation, and the first switching circuit is configured to electrically couple the first voltage source to the first signal line, the first bulks thereby having a first voltage value from the first voltage source;
- in the second, the third, or the fourth operational mode, the first switching circuit is configured to electrically couple the second voltage source to the first signal line, the first bulks thereby having a second voltage value from the second voltage source.
Dependencies are inferred from the claim text.