Electrical fuse bit cell

An electrical fuse (eFuse) memory array comprising:

• a plurality of eFuse bit cells, each eFuse bit cell of the plurality of eFuse bit cells having a first bit cell end, a second bit cell end, a third bit cell end, and a fourth bit cell end;
• a shared program transistor;
• a shared read transistor;
• and
• a read circuit,
• wherein
• each first bit cell end of each eFuse bit cell of the plurality of eFuse bit cells is coupled to the read circuit;
• each second bit cell end of each eFuse bit cell of the plurality of eFuse bit cells is coupled to the shared program transistor and the shared read transistor;
• each third bit cell end of each eFuse bit cell of the plurality of eFuse bit cells is configured to receive a program control line;
• and
• each fourth bit cell end of each eFuse bit cell of the plurality of eFuse bit cells is configured to receive a read control line.

A method comprising:

• in a program mode of an electrical fuse (eFuse) bit cell having a program transistor, a read transistor, and an eFuse having a first end and a second end,
• turning off the read transistor,
• turning on the program transistor, and
• configuring a program current to flow between the program transistor and the eFuse;
• and
• in a read mode of the eFuse bit cell,
• turning off the program transistor,
• turning on the read transistor, and
• configuring a read current to flow between the read transistor and the eFuse, and
• detecting a voltage value at a first terminal of the read transistor to determine a state of the eFuse,
• wherein a second terminal of the program transistor, a third terminal of the read transistor, and the first end of the eFuse are coupled together.

A method comprising:

• in a program mode of an eFuse bit cell to be programmed among a plurality of eFuse bit cells,
• turning off a shared read transistor,
• turning off a cell read transistor of the eFuse bit cell to be programmed,
• turning on a shared program transistor,
• turning on a cell program transistor of the eFuse bit cell to be programmed, and
• configuring a program current to flow between the shared program transistor, the cell program transistor of the eFuse bit cell to be programmed, and an eFuse of the eFuse bit cell to be programmed;
• and
• in a read mode of an eFuse bit cell to be read among the plurality of eFuse bit cells,
• turning off the shared program transistor,
• turning off a cell program transistor of the eFuse bit cell to be read,
• turning on the shared read transistor,
• turning on a cell read transistor of the eFuse bit cell to be read,
• configuring a read current to flow between the shared read transistor, the cell read transistor of the eFuse bit cell to be read, and an eFuse of the eFuse bit cell to be read, and
• detecting a voltage value at a first terminal of the cell read transistor of the eFuse bit cell to be read to determine a state of the eFuse of the eFuse bit cell to be read,
• wherein
• an eFuse bit cell of the plurality of eFuse bit cell includes a cell program transistor, a cell read transistor, and an eFuse,
• the cell program transistor, the cell read transistor, and a first end of the eFuse are coupled together;
• and
• the shared program transistor, the shared read transistor, and a second end of the eFuse are coupled together.