Semiconductor memory device and method for testing same
AssigneeElpida Memory, Inc.
InventorsYoshinori Matsui, Shoji Kaneko
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.
Claims18
A semiconductor device comprising:
- a data input/output terminal configured to supply write data in a normal write operation and to supply read data in a test mode;
- and
- an internal circuit configured to store the write data supplied by the data input/output terminal and to output the stored write data as the read data supplied the data input/output terminal;
- and
- a data latch circuit that captures and temporarily latches the write data supplied from the data input/output terminal in the normal write operation, latches the read data that is read from the internal circuit in response to a read operation in the test mode, and outputs the latched read data to the internal circuit in response to a write operation in the test mode.
A semiconductor device comprising:
- a data input/output terminal;
- an internal circuit;
- a data latch circuit that temporarily latches data captured from the data input/output terminal in a normal write operation, latches data read from the internal circuit in response to a read operation in a test mode, and outputs the latched data which is read from the internal circuit to the internal circuit in response to a write operation in the test mode;
- and
- an input circuit that sends data from the data input/output terminal to the data latch circuit, the input circuit turning on in the normal write operation and turning off in a normal read operation, wherein, in the test mode, the input circuit turns on in response to the read operation.
A semiconductor device comprising:
- a data input/output terminal configured to supply write data in a normal write operation, to supply read data in a normal read operation, and to supply the read data in a test mode;
- and
- an internal circuit configured to store the write data and output the write data as read data;
- a data latch circuit that latches the write data supplied from the data input/output terminal in the normal write operation without latching the read data that is read from the internal circuit in the normal read operation,
- wherein the data latch circuit latches the read data which is read from the internal circuit in response to a read operation in the test mode and outputs the latched read data to the internal circuit in response to a write operation in the test mode.
Dependencies are inferred from the claim text.