Non-volatile memory cell healing

A method, comprising:

• performing a quantity of program/erase cycles on a number of memory cells coupled in series between a first and a second select gate transistor;
• subsequently performing a healing operation on the number of cells based on the quantity of program/erase cycles reaching a first threshold quantity, the healing operation including:
• applying a healing voltage to a first edge memory cell;
• applying a healing voltage to a second edge memory cell;
• and
• applying a healing voltage to the non-edge memory cells;
• performing an erase operation on the number of cells subsequent to the healing operation and prior to performing an additional program/erase cycle on the number of cells;
• and
• performing a subsequent healing operation on the number of cells based on the quantity of program/erase cycles reaching a second threshold quantity, wherein the second threshold quantity is different than the first threshold quantity.

A method, comprising:

• performing a number of program and erase operations on a number of memory cells coupled in series between a first and a second select gate transistor;
• subsequently performing a healing operation on the number of cells in response to a reaching of a first threshold hot count, the healing operation including:
• applying a healing voltage to a first edge memory cell of the number of cells;
• applying a healing voltage to a second edge memory cell of the number of cells;
• and
• applying a healing voltage to the non-edge memory cells of the number of cells;
• wherein the healing voltage applied to at least one of the first edge memory cell, the second edge memory cell, and at least one non-edge memory cell increases a threshold voltage level of the memory cell to a level at or above an erase verify voltage level;
• and
• performing a subsequent healing operation on the number of memory cells in response to a reaching of a second threshold hot count, wherein the second threshold hot count is different than the first threshold hot count.

A device comprising:

• an array of memory cells including a number of subsets of cells coupled in series between a select gate source transistor and a select gate drain transistor;
• and
• control circuitry coupled to the array and configured to perform a healing operation on a number of the memory cells by:
• applying a first healing voltage to a first edge memory cell of a first subset of cells;
• applying a second healing voltage to a second edge memory cell of the first subset of cells;
• and
• applying at least a third healing voltage to a number of non-edge memory cells of the first subset;
• and
• wherein the healing operation is performed based on a quantity of program/erase cycles experienced by the number of memory cells;
• and
• wherein applying the at least a third healing voltage to the number of non-edge memory cells includes applying healing voltages higher in magnitude to those non-edge memory cells located closer to the first and second edge memory cells than to those non-edge memory cells located further from the first and second edge memory cells.

A method, comprising:

• performing a quantity of program/erase cycles on a number of memory cells coupled in series between a first and a second select gate transistor;
• subsequently performing a healing operation on the number of cells based on the quantity of program/erase cycles, the healing operation including:
• applying a healing voltage to a first edge memory cell;
• applying a healing voltage to a second edge memory cell;
• and
• applying a healing voltage to the non-edge memory cells;
• and
• performing an erase operation on the number of cells subsequent to the healing operation and prior to performing an additional program/erase cycle on the number of cells;
• wherein applying the healing voltage to the non-edge memory cells includes applying a healing voltage higher in magnitude to those non-edge memory cells located closer to the first and second edge memory cells than to those non-edge memory cells located further from the first and second edge memory cells.