Memory architecture having two independently controlled voltage pumps

A memory architecture, comprising:

• an array of non-volatile memory cells;
• a pair of independently controlled voltage pumps coupled to supply both a positive voltage bias and a negative voltage bias to the array during program and erase operations so that a sum of a magnitude of the positive and negative voltage biases is applied across a storage node of an accessed memory cell of the array;
• a plurality of register bits to store programmable values used by a plurality of voltage pumps to independently control the magnitudes of the positive and negative voltage biases;
• a control circuit coupled to the plurality of voltage pumps to control a duration of the positive and negative voltage biases;
• and
• a processor to determine and set the programmable values stored within the plurality of register bits and to supply a pump enable signal to the control circuit, wherein the processor is configured to adjust a duration of the pump enable signal based on a temperature measurement received from a temperature sensor.