Controlling select gate voltage during erase to improve endurance in non volatile memory
AssigneeSanDisk Technologies LLC
InventorsDeepanshu Dutta, Jeffrey W Lutze
Life of this patent
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Abstract
A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage.
Claims16
A method for performing an erase operation for erasing a set of non-volatile storage elements which is formed on a substrate, the set of non-volatile storage elements comprises one or more sets of series-connected non-volatile storage elements, each set of series-connected non-volatile storage elements is arranged between respective select gates, the method comprising:
- in a first time period, ramping up an erase voltage which is applied to the substrate from a non-zero initial level to a first level, and ramping up a voltage of at least one of the respective select gates from a non-zero starting level to a higher level in correspondence with the ramping up of the erase voltage, the ramping up the voltage of the at least one of the respective select gates comprises ramping up a voltage of a respective select gate driver of the at least one of the respective select gates from the non-zero starting level to the higher level while maintaining a pass gate which is between the respective select gate driver and the at least one of the respective select gates in a conductive state;
- and
- in a second time period which follows the first time period, driving the erase voltage at the first level while driving the voltage of the at least one of the respective select gates at the higher level, the driving the voltage of the at least one of the respective select gates at the higher level comprises driving the respective select gate driver at the higher level while maintaining the pass gate in the conductive state.
A non-volatile storage system, comprising:
- a set of non-volatile storage elements, formed on a substrate, the set of non-volatile storage elements comprises one or more sets of series-connected non-volatile storage elements, each set of series-connected non-volatile storage elements is arranged between respective select gates;
- and
- one or more control circuits, the one or more control circuits, to perform an erase operation to erase the set of non-volatile storage elements:
- in a first time period, ramp up an erase voltage which is applied to the substrate from a non-zero initial level to a first level, and cause a respective select gate driver of at least one of the respective select gates to ramp up a voltage of the at least one of the respective select gates from a non-zero starting level to a higher level in correspondence with the ramp up of the erase voltage while a pass gate which is between the respective select gate driver and the at least one of the respective select gates is in a conductive state, and in a second time period which directly follows the first time period, drive the erase voltage at the first level and cause the respective select gate driver to drive the voltage of the at least one of the respective select gates at the higher level.
A method for performing an erase operation for erasing a set of non-volatile storage elements which is formed on a substrate, the set of non-volatile storage elements comprises one or more sets of series-connected non-volatile storage elements, each set of series-connected non-volatile storage elements is arranged between respective select gates, the method comprising:
- in a first time period, ramping up an erase voltage which is applied to the substrate from a non-zero initial level to a maximum erase voltage level, while ramping up a voltage of a respective select gate driver of one of the respective select gates from a non-zero starting level to a maximum select gate level in correspondence with the ramping up of the erase voltage, and while maintaining a pass gate which is between the respective select gate driver and the one of the respective select gates in a conductive state;
- and
- in a second time period which directly follows the first time period, driving the erase voltage at the maximum erase voltage level while setting the voltage of the respective select gate driver at the maximum select gate level and while maintaining the pass gate in the conductive state.
Dependencies are inferred from the claim text.