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US 8,542,534 B2Granted
Select gate programming in a memory device
AssigneeMicron Technology, Inc.
InventorsShigekazu Yamada, Aaron Yip
Life of this patent
Estimating the term…
Abstract
Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.
Claims33
A method for programming select gate transistors, a different select gate transistor coupled to each end of a series string of memory cells, the method comprising:
- controlling an inhibit voltage on a data line coupled to a programmed select gate transistor;
- and
- applying a program voltage to a control gate of an unprogrammed select gate transistor wherein, once programmed, the select gate transistor is configured to control access to its respective series string of memory cells;
- and
- increasing the inhibit voltage by capacitive coupling between the data line and at least one other data line.
2 more elements
A method for programming select gate transistors, a different select gate transistor coupled to each end of a series string of memory cells, the method comprising:
- controlling an inhibit voltage on a data line coupled to a programmed select gate transistor;
- and
- applying a program voltage to a control gate of an unprogrammed select gate transistor wherein, once programmed, the select gate transistor is configured to control access to its respective series string of memory cells;
- wherein the program voltage comprises a plurality of program pulses having an incrementally increasing program voltage;
- and
- wherein the inhibit voltage is determined in response to a quantity of program pulses.
3 more elements
A method for programming select gate transistors, a different select gate transistor coupled to each end of a series string of memory cells, the method comprising:
- controlling an inhibit voltage on a data line coupled to a programmed select gate transistor;
- and
- applying a program voltage to a control gate of an unprogrammed select gate transistor wherein, once programmed, the select gate transistor is configured to control access to its respective series string of memory cells;
- wherein controlling the inhibit voltage further comprises controlling such that the inhibit voltage is both low enough to prevent a first voltage to a selected memory cell and high enough to allow a second voltage to the selected memory cell, such that the first voltage is greater than the second voltage.
1 more element
A method for programming a select gate transistor of a plurality of select gate transistors, each select gate transistor coupled to a different end of a respective series string of memory cells, the method comprising:
- applying a first voltage to a data line coupled to a select gate transistor, of the plurality of select gate transistors, to be program inhibited;
- increasing the first voltage to a second voltage that is greater than the first voltage by capacitive coupling with an adjacent data line;
- and
- applying programming pulses to the select gate transistor to be programmed wherein, once programmed, the select gate transistor is configured to control access to its respective series string of memory cells.
1 more element
A memory device comprising:
- a plurality of series strings of memory cells, each series string having a select gate transistor at each end;
- a plurality of data lines, each data line coupled to a different series string of memory cells through one of the select gate transistors;
- and
- a source line coupled to each of the series strings of memory cells through another one of the select gate transistors;
- wherein data lines coupled to select gate transistors to be program inhibited are configured to be biased at a voltage corresponding to a voltage provided by the source line.
2 more elements
A memory device comprising:
- a plurality of series strings of memory cells, each series string having a select gate transistor at each end;
- a plurality of data lines, each data line coupled to a different series string of memory cells through one of the select gate transistors;
- and
- a source line coupled to each of the series strings of memory cells through another one of the select gate transistors;
- wherein data lines coupled to select gate transistors to be program inhibited are configured to be biased at a voltage corresponding to a voltage provided by the source line;
- and
- wherein the source line is coupled to each of the plurality of data lines through a biasing transistor.
4 more elements
A memory device comprising:
- a plurality of series strings of memory cells, each series string having a select gate transistor at each end;
- a plurality of data lines, each data line coupled to a different series string of memory cells through one of the select gate transistors;
- a source line coupled to each of the series strings of memory cells through another one of the select gate transistors;
- and
- a series connection of transistors that enable access of a voltage to a memory cell;
- wherein data lines coupled to select gate transistors to be program inhibited are configured to be biased at a voltage corresponding to a voltage provided by the source line;
- and
- wherein the series connection of transistors comprises:
- a bias transistor for applying an initial voltage on a data line;
- a high voltage protection transistor coupled to the bias transistor for providing voltage protection to the data line;
- and
- a select transistor coupled between the high voltage protection transistor and the data line for selectively providing access to the data line;
- wherein a voltage on a control gate of the select transistor is controlled to provide access to the data line while the bias transistor and the high voltage protection transistor have control gate voltages that are only high enough to turn on their respective transistors.
10 more elements
A memory device comprising:
- a plurality of series strings of memory cells, each series string having a select gate transistor at each end;
- a plurality of data lines, each data line coupled to a different series string of memory cells through one of the select gate transistors;
- a source line coupled to each of the series strings of memory cells through another one of the select gate transistors;
- and
- a series connection of transistors that enable access of a voltage to a memory cell;
- wherein data lines coupled to select gate transistors to be program inhibited are configured to be biased at a voltage corresponding to a voltage provided by the source line;
- and
- wherein the series connection of transistors comprises:
- a bit line clamping transistor for applying an initial voltage on a data line;
- and
- a select transistor coupled between the bit line clamping transistor and the data line;
- wherein a voltage on control gate of the bit line clamping transistor is controlled to be a supply voltage while a voltage on a control gate of the select transistor is only high enough to turn on the select transistor.
9 more elements
A memory device comprising:
- a plurality of series strings of memory cells, each series string having a select gate transistor at each end;
- a plurality of data lines, each data line coupled to a different series string of memory cells through one of the select gate transistors;
- and
- a source line coupled to each of the series strings of memory cells through another one of the select gate transistors;
- wherein data lines coupled to select gate transistors to be program inhibited are configured to be biased at a voltage corresponding to a voltage provided by the source line;
- and
- wherein the voltage provided by the source line is increased for each step of a plurality of program inhibit steps wherein each different voltage is used to program inhibit programmed select gate transistors after a particular quantity of program pulses.
4 more elements
A memory device comprising:
- a memory array organized in series strings of memory cells, each of the strings having a select gate drain transistor coupled to a data line and a select gate source transistor coupled to a source line;
- and
- memory control circuitry coupled to the memory array for controlling operation of the memory array, the memory control circuitry configured to control programming of unprogrammed select gate drain transistors and/or unprogrammed select gate source transistors by selecting one of a plurality of inhibit voltages to be applied to each data line coupled to a programmed select gate drain transistor or a programmed select gate source transistor to be program inhibited;
- wherein the memory control circuitry is configured to select the one of the plurality of inhibit voltages in response to a number of program pulses applied to the unprogrammed select gate drain transistors and/or the unprogrammed select gate source transistors during programming.
1 more element
A memory device comprising:
- a memory array organized in series strings of memory cells, each of the strings having a select gate drain transistor coupled to a data line and a select gate source transistor coupled to a source line;
- and
- memory control circuitry coupled to the memory array for controlling operation of the memory array, the memory control circuitry configured to control programming of the select gate drain transistors and/or the select gate source transistors by selecting one of a plurality of inhibit voltages to be applied to each data line coupled to a select gate drain or a select gate source transistor to be program inhibited;
- wherein the memory control circuitry is further configured to control application of the selected inhibit voltage to a selected data line by control of a bias transistor coupled to an unselected data line adjacent to the selected data line such that the bias transistor transfers a voltage from the source line to the unselected data line that is capacitively coupled to the adjacent selected data.
1 more element
A memory device comprising:
- a memory array organized in series strings of memory cells, each of the strings having a select gate drain transistor coupled to a data line and a select gate source transistor coupled to a source line;
- and
- memory control circuitry coupled to the memory array for controlling operation of the memory array, the memory control circuitry configured to control programming of the select gate drain transistors and/or the select gate source transistors by selecting one of a plurality of inhibit voltages to be applied to each data line coupled to a select gate drain or a select gate source transistor to be program inhibited;
- wherein the memory control circuitry is further configured to control programming of the select gate source transistors by increasing a voltage applied to both the select gate drain transistors and the memory cells prior to generation of a programming pulse on the select gate source transistors.
1 more element
A memory device comprising:
- a memory array organized in series strings of memory cells, each of the strings having a select gate drain transistor coupled to a data line and a select gate source transistor coupled to a source line;
- and
- memory control circuitry coupled to the memory array for controlling operation of the memory array, the memory control circuitry configured to control programming of the select gate drain transistors and/or the select gate source transistors by selecting one of a plurality of inhibit voltages to be applied to each data line coupled to a select gate drain or a select gate source transistor to be program inhibited;
- wherein the memory control circuitry is further configured to select each of the plurality of inhibit voltages in sequence from a low inhibit voltage to a high inhibit voltage prior to generating a programming pulse while the high inhibit voltage is applied to each data line to be program inhibited.
1 more element
A method comprising:
- biasing, at a first voltage, a data line coupled to a select gate to be program inhibited;
- and
- biasing a source line voltage at a second voltage, wherein a data line adjacent to the data line coupled to the select gate to be program inhibited is pulled up to the second voltage, and wherein the data line coupled to the select gate to be program inhibited is pulled up to an inhibit voltage responsive to the adjacent data line being pulled up to the second voltage.
Dependencies are inferred from the claim text.