Memory access method and flash memory using the same

A flash memory, comprising:

• a sense unit;
• an NAND memory array, comprising a plurality of memory cells, wherein the memory cells are arranged into a plurality of streams, which are globally controlled with a string select signal;
• and
• a memory controller, coupled to the NAND memory array, the memory controller further determining a setup phase and a read phase, which does not overlap with the setup phase, wherein,
• the memory controller provides a stream bias signal on a selected stream among the plurality of streams and provides a selected word line signal on a selected cell of the selected stream, in a setup phase;
• the memory controller further provides a plurality of unselected word line signals on the rest of memory cells, to have the rest of memory cells turned on as pass transistors, in the setup phase;
• the memory controller further provides a discharge path connected to the plurality of streams to accordingly eliminate coupling charge presented on at least an unselected stream among the plurality of streams, in the setup phase;
• and
• the memory controller further enables the string select signal to have the selected stream connected to the sense unit via a metal bit line, so that the sense unit accordingly reads the selected cell in a voltage sensing scheme, in the read phase.