Back to results
US 8,542,514 B1Granted
Memory structure having SRAM cells and SONOS devices
AssigneeCypress Semiconductor Corporation
InventorsSethuraman Lakshminarayanan, Myongseob Kim
Life of this patent
Estimating the term…
Abstract
A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.
Claims10
A memory structure, comprising:
- a first memory cell having a first plurality of non-volatile Semiconductor-Oxide-Nitride-Oxide-Semiconductor type (SONOS-type) devices coupled with a first Six Transistor (6-T) Static Random Access Memory (SRAM) cell;
- a second memory cell having a second plurality of non-volatile SONOS-type devices coupled with a second 6-T SRAM cell, wherein the first plurality of non-volatile SONOS-type devices are interdigitated with the second plurality of non-volatile SONOS-type devices;
- a store gate line, a non-volatile gate line, and a recall gate line, wherein the store gate line, the non-volatile gate line, and the recall gate line overlap diffusion areas of both the first and second pluralities of non-volatile SONOS-type devices;
- and
- wherein each of the first and the second pluralities of non-volatile SONOS-type devices comprises an interconnect and a set of dummy interconnects.
2 more elements
A method for fabricating a memory structure, comprising:
- forming a first memory cell having a first plurality of non-volatile Semiconductor-Oxide-Nitride-Oxide-Semiconductor type (SONOS-type) devices coupled with a first Six Transistor (6-T) Static Random Access Memory (SRAM) cell;
- forming a second memory cell having a second plurality of non-volatile SONOS-type devices coupled with a second 6-T SRAM cell, wherein the first plurality of non-volatile SONOS-type devices are interdigitated with the second plurality of non-volatile SONOS-type devices;
- forming a store gate line, a non-volatile gate line, and a recall gate line, wherein each of the store gate line, the non-volatile gate line, and the recall gate line overlaps diffusion areas of both the first and second pluralities of non-volatile SONOS-type devices;
- and
- forming a plurality of interconnects and a plurality of dummy interconnects, wherein each of the first and second pluralities of non-volatile SONOS-type devices is coupled with one of the plurality of interconnects and one of the plurality of dummy interconnects.
2 more elements
Dependencies are inferred from the claim text.