Gate pulse modulating circuit and method

A gate pulse modulating circuit, comprising:

• a timing controller, generating an output enable signal and multiple time control signals;
• a high gate voltage generating unit, electrically connected to timing controller and for receiving the time control signals, and generating a high gate voltage with a waveform including a plurality of cutting edges in response to the time control signals;
• a low gate voltage generating unit, generating a low gate voltage;
• and
• a gate driver, electrically connected to the timing controller for receiving the output enable signal, the high gate voltage generating unit for receiving the high gate voltage and the low gate voltage generating unit for receiving the low gate voltage, and generating a plurality of gate pulses in response to a plurality of enable periods of the output enable signal;
• wherein a waveform of the gate pulses includes a plurality of cutting edges;
• wherein the time control signal comprises a first time control signal, a second time control signal, a third time control signal and a fourth time control signal, and the high gate voltage generating unit comprises:
• a first capacitor, having a first end to receive a maximum voltage and a second end capable of a first voltage;
• a second capacitor, having a first end capable of receiving a maximum voltage and a second end to receive a second voltage;
• a third capacitor, having a first end to receive the second voltage and a second end to receive a third voltage;
• a fourth capacitor, having a first end to receive the third voltage and a second end to receive a ground voltage;
• a first resistor, having a first end connected to a high gate voltage output;
• a second resistor, having a first end connected to a second end of the first resistor;
• a third resistor, having a first end connected to a second end of the second resistor;
• a first switching unit, connected between the first end of the first capacitor and the first end of the first resistor;
• a second switching unit, connected between the first end of the second capacitor and the first end of the second resistor;
• a third switching unit, connected between the first end of the third capacitor and the first end of the third resistor;
• and
• a fourth switching unit, connected between the first end of the fourth capacitor and the second end of the third resistor;
• wherein the first switching unit is controlled by the first time control signal, the second switching unit is controlled by the second time control signal, the third switching unit is controlled by the third time control signal and the fourth switching unit is controlled by the fourth time control signal, the maximum voltage is greater than the first voltage, the first voltage is greater than the second voltage, and the second voltage is greater than the third voltage.

A gate pulse modulating method, comprising steps of:

• generating an output enable signal, a first time control signal and a second time control signal by a timing controller;
• generating a high gate voltage varying among a maximum voltage, a first voltage, and a second voltage by a high gate voltage generating unit;
• and
• providing a gate driver capable of generating a gate pulse in response to the high gate voltage;
• wherein a level transition relationship of the output enable signal, the first time control signal and the second time control signal is:
• the output enable signal has a level transition at a time point t1, the first time control signal has a level transition at a time point t2, the second time control signal has a level transition at a time point t3, the output enable signal has a level return at a time point t4, the second time control signal has a level return at a time point t5, and the first time control signal has a level return at a time point t6;
• wherein the high gate voltage is maintained at the high level between the time point t1 and the time point t2;
• the high gate voltage drops from the maximum voltage to the first voltage between the time point t2 and the time point t3;
• the high gate voltage drops from the first voltage to the second voltage between the time point t3 and the time point t5;
• the high gate voltage rises from the second voltage to the first voltage between the time point t5 and the time point t6;
• and the high gate voltage rises from the first voltage to the maximum voltage after the time point t6.

A gate pulse modulating method, comprising steps of:

• generating an output enable signal, a first time control signal, a second time control signal, a third time control signal and a fourth time control signal by a timing controller;
• generating a high gate voltage varying among a maximum voltage, a first voltage, a second voltage and a third voltage by a high gate voltage generating unit;
• and
• providing a gate driver to generate a gate pulse in response to the high gate voltage;
• wherein a level transition relationship of the output enable signal, the first time control signal, the second time control signal, a third time control signal and the fourth time control signal is:
• the fourth time control signal has a level transition at a time point t1, the third time control signal has a level transition at a time point t2, the second time control signal has a level transition at a time point t3, the first time control signal has a level transition at a time point t4, the output enable signal has a level transition at a time point t5, the first time control signal has a level return at a time point 6, the second time control signal has a level return at a time point t7, the third time control signal has a level return at a time point t8, and the fourth time control signal and the output enable signal have a level return respectively at a time point t9.