Data driving apparatus and display device comprising the same

A data driving apparatus comprising:

• a horizontal synchronization start signal generation circuit that generates a horizontal synchronization start signal when at least two last bits of image data signals are a same logic level, the horizontal synchronization start signal being derived from the at least two last bits, the horizontal synchronization start signal generation circuit including a plurality of flip-flops that are connected to one another in a cascade manner, supplied with and sequentially outputting the image data signals, and an operation unit that performs a logical operation on output signals supplied from at least two flip-flops among the plurality of flip-flops to generate the horizontal synchronization start signal, wherein the logical operation indicates whether all of the output signals supplied from the at least two flip-flops to the operation unit have a same logic level;
• a shift register that samples the image data signals in response to the horizontal synchronization start signal and a data sampling clock signal, and outputs the sampled image data signals in response to a load signal;
• a digital-to-analog converter that receives the sampled image data signals from the shift register and outputs a plurality of analog data signals corresponding to the sampled data signals;
• and
• a buffer that is supplied with the plurality of analog data signals, selects polarities of the analog data signals and provides the selected polarities to the data signals,
• wherein the horizontal synchronization start signal generation circuit is disabled in response to the load signal.

A display device comprising:

• a display panel that includes a plurality of unit pixels at intersections of a plurality of gate lines and a plurality of data lines;
• a timing controller that provides data control signals and image data signals;
• and
• a data driver that applies data signals to the plurality of data lines in response to the data control signals and the image data signal, the data driver comprising:
• a horizontal synchronization start signal generation circuit that generates a horizontal synchronization start signal from an output of a logical operation performed on image data signals, wherein the horizontal synchronization start signal is generated when the logical operation indicates that at least two last bits of the image data signals are a same logic level, the horizontal synchronization start signal being an output of the logical operation;
• and
• a data driving circuit that samples the image data signals in response to the horizontal synchronization start signal and supplies a plurality of data signals using the sampled image data signals in response to a load signal,
• wherein the horizontal synchronization start signal generation circuit is disabled in response to the load signal.