Pipelined ADC stage filters
AssigneeCrest Semiconductors, Inc.
InventorsYusuf Haque, Ryan James Kier, Rex K. Hales, Paul Talmage Watkins, Marcellus C. Harper
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Abstract
A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.
Claims20
A pipelined Analog-to-Digital Converter (ADC) stage comprising:
- a main sampling path comprising a first filter in series with a first sample and hold circuit;
- and
- a sub-ADC sampling path comprising a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC);
- wherein a frequency response of said main sampling path is matched to a frequency response of said sub-ADC sampling path such that a residue signal of said pipelined ADC stage stays within range.
A method for operating a pipelined Analog-to-Digital Converter (ADC) stage, the method comprising:
- sampling an input signal with a main sampling path comprising a first snubbing filter and a Multiplying-Digital-to-Analog Converter (MDAC);
- and
- sampling said input signal with a sub-ADC sampling path comprising a second filter and a sub-ADC connected to said MDAC;
- wherein a frequency response of said main sampling path is matched to a frequency response of said sub-ADC sampling path such that a residue signal of said pipelined ADC stage stays within range.
A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, a first stage comprising:
- a signal input connected to a main sampling path comprising a first snubbing filter between said signal input and a Multiplying-Digital-to-Analog Converter (MDAC);
- and
- a sub-ADC sampling path comprising a second filter between said signal input and a sub ADC connected to said MDAC, said sub-ADC sampling path also connected to said signal input;
- wherein a frequency response of said main sampling path is matched to a frequency response of said sub-ADC sampling path such that a residue signal of said pipelined ADC stage stays within range and a frequency response of said sub-ADC is not matched with a frequency response of said main sampling path.
Dependencies are inferred from the claim text.